Lam Research Corporation

Applied Materials, Inc.

Qian Fu

Zhongkui Tan

Ying Wu

Qing Xu

John Stephen Drewery

Wonchul Lee

Shenjian Liu

Hua Xiang

Alex Paterson

Yoko Yamaguchi

Hyun-Yong Yu

Maolin Long

Ce Qin

Bryan Y Pu

Yiting Zhang

Youn Gi Hong

Shih-Yuan Cheng

Mark Joseph Saly

Hong Shih

Jeffrey W Anthis

Mirzafer K Abatchev

Duane Outka

Tuochuan Huang

David Knapp

Aaron Eppler

Yifeng Zhou

Raphael Casaes

Hailong Zhou

Zhonghua Yao

Jayoung Choi

Lin Cui

Abhijeet S Bagal

Huai-Yu Hsiao

In Deog Bae

Yang Yang

Andrew D Bailey, Iii

Deenesh Padhi

Mukund Srinivasan

Katrina Mikhaylichenko

Saravanapriyan Sriraman

Mark Henry Wilcoxson

Tomohiko Kitajima

Takehito Koshizawa

Gill Yong Lee

Tong Liu

Tom A Kamp

Sung-Kwan Kang

Hang Yu

Chang Seok Kang

Rajesh Sathiyanarayanan

Yoshie Kimura

Fredrick Fishburn

Ganesh Upadhyaya

Marcus Musselman

Qinghua Zhong

Chung Liu

Linda B Braly

Chuanxi Yang

Yasushi Ishikawa

Lin Zhao

Xiawan Yang

Glenn W Gale

Amit Jain

Kuan-Ting Liu

Gladys Lo

Juan Valdivia, Iii

Tae Won Kim

Denis Syomin

Linda Fung-Ming Lee

Sam Do Lee

Martin Shim

Sangjun Park

Sung Jin Jung

Yansha Jin

Yeonju Kwak

Jeong Hwan Kim

Siyu Zhu

Feng Qiao

Junkai He

Radhe Agarwal

Wenbing Hu

Indeog Bae

I C Jang

A method includes providing, within an etch chamber, a base structure including a target layer disposed on a substrate, and an etch mask disposed on the target layer, dry etching, within the etch chamber, the target layer using thionyl chloride to obtain a processed base structure, and after forming the plurality of features. The processed base structure includes a plurality of features and a plurality of openings defined by the etch mask. The method further includes removing the processed base structure from the etch chamber. In some embodiments, the target layer includes carbon. In some embodiments, the dry etching is performed at a sub-zero degree temperature.

Dry etching with etch byproduct self-cleaning

A method and system for etching high aspect ratio structures in a semiconducting processing chamber are disclosed herein. In one example, a method of patterning a substrate comprises etching the substrate to form a recess, depositing a passivation layer on sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etch forms a recess to a first depth, the substrate having a mask layer disposed thereon. The treating of the passivation layer is for removal of a clogging material formed from an etch byproduct on the mask layer. The etching the recess to a second depth while maintaining a minimum variation of a recess sidewall width.

Method for etching high aspect ratio structures

Systems and methods for reverse pulsing are described. One of the methods includes receiving a digital signal having a first state and a second state. The method further includes generating a transformer coupled plasma (TCP) radio frequency (RF) pulsed signal having a high state when the digital signal is in the first state and having a low state when the digital signal is in the second state. The method includes providing the TCP RF pulsed signal to one or more coils of a plasma chamber, generating a bias RF pulsed signal having a low state when the digital signal is in the first state and having a high state when the digital signal is in the second state, and providing the bias RF pulsed signal to a chuck of the plasma chamber.

Systems and methods for reverse pulsing

Exemplary semiconductor processing methods may include depositing a boron-containing material on the substrate. The boron-containing material may extend along sidewalls of the one or more features in the substrate. The methods may include forming a plasma of an oxygen-containing precursor and contacting the substrate with plasma effluents of the oxygen-containing precursor. The contacting may etch a portion of the one or more features in the substrate. The contacting may oxidize the boron-containing material.

Sidewall passivation for plasma etching

A method includes performing a dry etch process to remove a portion of a first layer disposed on a second layer of a stack of alternating layers. The first layer includes a first material and the second layer includes a second material different from the first material, and the dry etch process forms a passivation layer including a byproduct on surfaces of the second material. A amount of first material of the portion of the first layer remains after performing the dry etch process, The method further includes introducing a halide gas to enhance the passivation layer on the surfaces of the second material.

Enhanced etch selectivity using halides

Exemplary semiconductor processing methods may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may define one or more recessed features. The methods may include providing a second precursor to the processing region. The methods may include forming a plasma of the carbon-containing precursor and the second precursor in the processing region. Forming the plasma of the carbon-containing precursor and the second precursor may be performed at a plasma power of greater than or about 500 W. The methods may include depositing a carbon-containing material on the substrate. The carbon-containing material may extend within the one or more recessed features. The methods may include, subsequent depositing the carbon-containing material for a first period of time, applying a bias power while depositing the carbon-containing material for a second period of time.

Carbon gap fill processes

A substrate is disposed on a substrate holder within a process module. The substrate includes a mask material overlying a target material with at least one portion of the target material exposed through an opening in the mask material. A plasma is generated in exposure to the substrate. For a first duration, a bias voltage is applied at the substrate holder at a first bias voltage setting corresponding to a high bias voltage level. For a second duration, after completion of the first duration, a bias voltage is applied at the substrate holder at a second bias voltage setting corresponding to a low bias voltage level. The second bias voltage setting is greater than 0 V. The first and second durations are repeated in an alternating and successive manner for an overall period of time necessary to remove a required amount of the target material exposed on the substrate.

Methods and systems for advanced ion control for etching processes

Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Selection gate separation for 3D NAND

Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.

Selective carbon deposition on top and bottom surfaces of semiconductor substrates

Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include one or more patterned features separated by exposed regions of the substrate. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor. Forming the plasma of the silicon-containing precursor and the hydrogen-containing precursor may be performed at a plasma power of less than or about 1,000 W. The methods may include depositing a silicon-containing material on the one or more patterned features along the substrate. The silicon-containing material may be deposited on the patterned features at a rate of at least 2:1 relative to deposition on the exposed regions of the substrate.

Selective silicon deposition

Described herein is a method for etching a sample. The method includes performing a plasma etch pulse. The plasma etch pulse is performed by directing a gas flow comprising silicon tetrachloride (SiCl) and a diluent towards the sample. While directing the gas flow, a bias power is applied to achieve a bias state for a first time period. Then, a source power is applied to achieve a source state for a second time period, and then no bias power and no source power is applied to achieve a recovery state for a third time period. The plasma etch pulse is repeated until a target amount of the sample is etched.

Pulsed etch process

Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.

Boron nitride for mask patterning

Systems and methods for reverse pulsing are described. One of the systems includes a controller, first and second source radio frequency (RF) generators, and first and second bias RF generators. The controller controls the first source RF generator to generate a first source pulsed signal, and controls the second source RF generator to generate a second source pulsed signal. The system includes a first match circuit that receives the first and second source pulsed signals and combines the first and second source pulsed signals. The controller controls the first bias RF generator to generate a first bias pulsed signal, and controls the second bias RF generator to generate a second bias pulsed signal. The system includes a second match circuit that receives the first and second bias pulsed signals and combines the first and second bias pulsed signals into a combined bias signal.

Systems for reverse pulsing

A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiOlayer and etching a SiN layer. Etching a SiOlayer comprises flowing a SiOetching gas into the plasma processing chamber, wherein the SiOetching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SFand NF, generating a plasma from the SiOetching gas, providing a bias, and stopping the SiOlayer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.

Silicon oxide silicon nitride stack stair step etch

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Pleasanton, CA, United States of America

Qian Fu