Xilinx, Inc.

Qi Zhang

Jian Tan

Jason R Bergendahl

Guo Jun Ren

Atul V Ghia

Ketan Sodha

Suresh M Menon

Wenfeng Zhang

Prasad Rau

Venu M Kondapalli

Matthew H Klein

Paul T Sasaki

Terence J Magee

Richard William Swanson

Hassan K Bazargan

Srinivas Vura

An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

Recalibration of source synchronous systems

Embodiments of a method, apparatus and circuit for voltage regulation are disclosed. One embodiment of a circuit includes a first field effect transistor (FET) having a gate, a drain and a source. A current source is connected to the drain of the FET. A second FET has a source connected to the source of the first FET by a node. The second FET also has a gate. A low-pass filter circuit has an input connected to the gate of the first FET and an output connected to the gate of the second FET.

Voltage regulator

A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device

A system for signal level shifting in an IC can include a first inverter having a first pull-up device and a pull-down device, wherein the first inverter is operable to receive an input signal having a voltage potential at a logic high that does not disable the first pull-up device. The system can include a second inverter coupled in series to an output of the first inverter, and a control module coupled to the output of the first inverter and an output of the second inverter. Prior to the input signal transitioning to the logic high, the control module is operable to decouple the input signal from the first pull-up device, disable the first pull-up device, and close a feedback loop that latches an output state of the second inverter.

High speed, low power signal level shifter

A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device. Edge boosting modules are employed to improve performance during reduced output common mode voltage modes of operation.

An output circuit providing an adjustable output amplitude and common-mode voltage is described. The output circuit includes at least one driver circuit and a common-mode feedback circuit including a first replica circuit of the at least one driver circuit. The common-mode feedback circuit is coupled to receive a first bias and provide an output coupled to the at least one driver circuit. The output circuit may also include a current circuit having a configurable resistor and a second replica circuit of the at least one driver circuit. The current circuit may be coupled to receive a second bias and to provide an output coupled to the at least one driver circuit and the common-mode feedback circuit.

Methods and apparatus for implementing an output circuit

An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.

Reversible input/output delay line for bidirectional input/output blocks

A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.

Data alignment and deskewing module

Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit () includes a synchronization circuit () coupled to receive a reference signal () and configured to provide a derivative signal (). A phase lock detector () is coupled to receive the reference signal () and the derivative signal () and is configured to provide a cycle lock signal () indicating whether a phase lock exists within a lock window () for a clock cycle.

Phase lock detector

A high-speed, area-efficient level shifter includes transistors having a variety of oxide thicknesses. The level shifter has a protection circuit stage, and a current mirror stage that allows the level shifter to perform over a wide voltage range at a high frequency. The level shifter maintains rise time, fall time, and duty cycle over a wide range of input and output voltage levels.

Voltage level shifter

A level translator includes a programmable booster stage that augments the drive level of the level translator under certain conditions. The booster stage is programmably activated. e.g., via a memory cell or control bit, and augments operation of the pull-up stages of a cross-coupled latch within the level translator. When the voltage levels at the high voltage portion of the level translator are reduced below a threshold voltage, the booster stage is activated to maintain proper operation of the level translator despite the reduced voltage levels.

Method and apparatus for a programmable level translator

A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

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Chandler, AZ, United States of America

Qi Zhang