Intel Corporation

Qi Zeng

Helia A Naeimi

Provided are an apparatus, system, integrated circuit die, and method for caching data in a hierarchy of caches. A first cache line in a first level cache having modified data for an address is processed. Each cache line of cache lines in the first level cache store data for one of a plurality of addresses stored in multiple cache lines of a second level cache. A second cache line in the second level cache is selected and a determination is made of a number of corresponding bits in the first cache line and the second cache line that are different. Bits in the first cache line that are different from the corresponding bits in the second cache line are written to the corresponding bits in the second cache line in response to a determination that the number of corresponding bits that are different is less than a threshold.

Apparatus, system, integrated circuit die, and method to determine when to bypass a second level cache when evicting modified data from a first level cache

Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory device. An incoming cache line is read from the second memory device. A plurality of cache lines in the first memory device are processed to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line. Bits from the incoming cache line that are different from the bits in the eviction cache line are written to the eviction cache line in the first memory device.

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Santa Clara, CA, United States of America

Qi Zeng