Stmicroelectronics (shenzhen) R&d Co. Ltd.

Stmicroelectronics S.r.l.

Qi Yu Liu

Ru Feng Du

Hong Wu Lin

Dario Arena

Yu Yong Wang

Ignazio Pisello

In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.

Deglitching circuit and method in a class-D amplifier

A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.

Electronic circuit and corresponding method of testing electronic circuits

Deglitching circuit and method in class-D amplifier

A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

Methods and circuits to reduce pop noise in an audio device

A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.

High efficiency class D amplifier with reduced generation of EMI

A class-D audio amplifier incorporates an overcurrent protection scheme implementing two overcurrent thresholds to avoid a dynamic impedance drop. When output current reaches the first threshold as a result of an impedance drop across the speaker, the overcurrent protection circuitry limits the output current to the value of the first threshold, but does not shut down the circuit. The second threshold is used to detect an overcurrent condition to shut down the circuit. Current limiting logic of a first channel monitors the overcurrent condition of a second channel and controls the first channel output in response thereto. This permits the second channel output current to reach the second threshold if the circuit is experiencing a short-circuit condition. This scheme also allows the output current to drop below the first threshold if the overcurrent condition of the second channel is caused by an impedance drop across the output speaker.

Advanced current limit function for audio amplifier

A Class-D amplifier includes a pre-amplifier having an input configured to receive an amplifier reference voltage signal which is ramped at start-up at a fast rate. An integrator has a first input configured to receive an input signal from the pre-amplifier and a second input configured to receive an integrator reference voltage signal which is ramped at start-up at a slower rate. A modulator has an input coupled to an output of the integrator. The modulator generates a pulse width modulated output signal. Operation of the Class-D amplifier is controlled at start-up by applying a slow ramped signal as the integrator reference voltage signal and a fast ramped signal as the amplifier reference voltage so that the pulse width modulated output signal exhibits an increasing change in duty cycle in response to an increasing voltage of the integrator reference voltage signal, and no 'pop' is introduced at start-up.

Growing community of inventors

Shenzhen, China

Qi Yu Liu