Cadence Design Systems, Inc.

Cisco Technology, Inc.

Amo Manufacturing Usa, LLC

Qi Wang

Vivek Chickermane

Guang-ming Dai

Pinhong Chen

Ankur Gupta

Huan-Chih Tsai

Christina Chu

Steven Sharp

Yonghao Chen

Francois Le Faucheur

Anatoly Fabrikant

Manish Pandey

Patrick Gallagher

Sandeep Bhatia

Mitchell W Hines

Sumit Roy

Sourav Nandy

Tim DeVreese

Ranganathan Sankaralingam

Yonghoa Chen

Ben Logan

In one embodiment a system component in a content delivery network (CDN), the CDN including a request router and edge caches, the request router being operable to determine which edge cache should serve content to a client, the system competent including a processor, and a memory to store data used by the processor, wherein the processor is operative to receive a request for content from the client, and based on a decision to shut down a first edge cache after the client has already downloaded some of the content from the first edge cache, participate in a process to transfer the client from downloading the content from the first edge cache to downloading the content from a second edge cache in the middle of the client downloading the content so that the client continues downloading the content from the second edge cache. Related apparatus and methods are also described.

CDN scale down

A disclosed method is performed at a system configured to distribute segment instances corresponding to segments of a media item. The method includes receiving, from a client device, a first segment request including data indicative of a first set of segments of the media item and data indicative of a first bitrate. The method further includes transmitting, to the client device in response to the first segment request, a first set of segment instances, each of the first set of segment instances including data encoding a respective one of the first set of segments at the first bitrate. The method includes generating, in response to the first segment request, a first prediction indicative of a first predicted set of segment instances, each of the first predicted set of segment instances including data encoding a segment of the media item subsequent to the first set of segments at one of a plurality of predicted bitrates.

Predictive media distribution system

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Method and mechanism for implementing electronic designs having power information specifications background

A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.

High level IC design with power specification and power source hierarchy

Method and system for conducting low-power design explorations are disclosed. The method includes receiving an RTL netlist of a circuit design, creating one or more power requirement files, wherein each power requirement file comprises power commands corresponding to the RTL netlist, generating one or more low-power RTL netlists using the corresponding one or more power requirement files and the RTL netlist, and conducting low-power design explorations using the one or more low-power RTL netlists.

Method and system for conducting a low-power design exploration

A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and the cell's rate of output voltage change; ordering the cells of the plurality based upon the values; identifying a difference between values of cells that are proximate each other within the ordering of the cells that meets a threshold; and designating a cut point within the ordering of the cells based upon the identified difference.

Selection of cells from a multiple threshold voltage cell library for optimized mapping to a multi-Vt circuit

A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circuit design; mapping a portion of the first block to a cell in the first cell library based upon the at least one constraint in view of a step of mapping a portion of the second block to a cell in the second cell library; and mapping a portion of the second block to a cell in the second cell library based upon the at least one constraint in view of the step of mapping a portion of the first block to a cell in the first cell library.

Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass

The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques may be identified. Then, the one or more candidates may be marked with the one or more optimization techniques within the micro-electronic circuit without altering the data and/or control paths of the circuit. Then, after timing and logic optimization, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique is reducible, and if so, then the technique may be reduced to determine whether such reduction improves the circuit's timing.

Method and mechanism for RTL power optimization

A method and system are provided for computing behavioral level observabilities of a digital system. In one example, a logic network is provided for performing an observability analysis at the behavioral level of a digital system. The logic network includes logic objects configured to emulate behavioral observabilities computed from a control data flow graph (CDFG), wherein the logic objects include at least one of: first logic objects configured to compute a token observable condition (TOC) of an edge of the CDFG; and second logic objects configured to compute a node observable condition (NOC) of a node of the CDFG. A logic optimization is used to optimize the logic network to obtain an optimized logic network of the behavioral observabilities.

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San Jose, CA, United States of America

Qi Wang