Samsung Electronics Co., Ltd.

Qi Wang

Kwang-Jin Lee

Chang-Soo Lee

Hye-Jin Kim

Joon-Min Park

Taek-Sung Kim

Hui-kwon Seo

Woo-Yeong Cho

Kwang-Ho Kim

Hyun-Ho Choi

Yong-Jun Lee

Du-Eung Kim

Kwangho Kim

Sang-beom Kang

Won-Seok Lee

Kwang Jin Lee

Kwangjin Lee

Wooyeong Cho

Beak Hyung Cho

Hyunho Choi

Yong-jin Yoon

Joon Yong Choi

A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Memory device and system with improved erase operation

Method of erasing a memory including first and second erase modes

In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.

Semiconductor device having resistance based memory array and method of operation associated therewith

Memory device using a variable resistive element

In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

Semiconductor device having memory array, method of writing, and systems associated therewith

Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Variable resistance memory device and system

A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

Input circuit of a non-volatile semiconductor memory device

A multi-port phase change random access memory (PRAM) cell, includes a PRAM element including a phase change material, a writing controller configured to operate in correspondence with a writing word line, the writing controller connecting a writing bit line to the PRAM element, and a reading controller configured to operate in correspondence with a reading word line, the reading controller connecting the PRAM element to a reading bit line.

Multi-port phase change random access memory cell and multi-port phase change random access memory device including the same

A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.

Nonvolatile memory device and related method of operation

Growing community of inventors

Suwon-si, South Korea

Qi Wang