Micron Technology Incorporated

Qi Dong

Poorna Kale

Lei Pan

Christopher Joseph Bueb

Te-Chang Lin

Xuesong Li

Exemplary methods, apparatuses, and systems include an update performance manager for controlling performance of a wireless update by adjusting prioritization of internal operations for a memory subsystem. The update performance manager receives a first notification representing an initialization of a file transfer that includes an update file from a host using wireless communication. The update performance manager enters an update mode by reducing a priority of at least one internal operation of the memory subsystem in response to the first notification. The update performance manager receives the update file. The update performance manager programs the update file to memory. The update performance manager receives a second notification being a completion of the file transfer. The update performance manager resetting the priority of the at least one internal operation of the memory subsystem to a default value in response to the second notification.

Performance management using intelligent prioritization of memory operations

A system for providing memory chip test pad access management to facilitate data security is disclosed. A host issues a command to access a non-volatile memory of a memory chip system via a test pad. A controller acknowledges the command by transmitting a response to the host to authenticate the host for access. The host then issues an authenticated command to modify a reserved byte of a protected memory partition of the non-volatile memory. The controller responds to the authenticated command and the reserved byte is modified. Firmware of the memory chip system monitors the modification of the reserved byte and notifies the memory chip system to activate a switch in an access control unit controlling access to the non-volatile memory. The switch is then activated, thereby closing a circuit to connect the test pad with the non-volatile memory. The host then access the non-volatile memory via the test pad.

Memory chip test pad access management to facilitate data security

Apparatuses, systems, and methods for buffer threshold monitoring to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include buffering data in a first memory device, writing the buffered data from the first memory device to a second memory device, determining that the first memory device is storing at least a threshold amount of data, and sending a first signal to the second memory device in response to determining that the first memory device is storing at least the threshold amount of data, wherein the first signal causes the second memory device to enter an increased write performance mode.

Buffer threshold monitoring to reduce data loss

The present disclosure includes apparatuses, methods, and systems for storing non-volatile memory initialization failures. In an example, a method can include initializing a volatile memory die, initializing a first non-volatile memory die in response to initializing the volatile memory die, copying executable instructions from the first non-volatile memory die to the volatile memory die in response to initializing the first non-volatile memory die, initializing the second non-volatile memory die in response to initializing the first non-volatile memory die, and storing a failure record in the first non-volatile memory die in response to an error occurring during the initialization of the second non-volatile memory die.

Storing non-volatile memory initialization failures

Methods, apparatuses, and non-transitory machine-readable media associated with a memory device training are described. An apparatus for memory device training can include a memory device and a processing device communicatively coupled to the memory device. The processing device can be configured to perform a plurality of training rounds associated with performance of the memory device at different temperatures and different voltages and write results of the plurality of training rounds to a plurality of mode registers of the memory device. The processing device can also be configured to log an initial group identifier into a current GID MR as a reference identifier and in response to a threshold deviation from the reference ID or in response to lack of deviation outside the threshold for a threshold amount of time, retrieve an updated training setting from the results in the plurality of mode registers and enable the updated training setting.

Memory device training

Technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.

Multi-partition file system for storing video streams in a managed non-volatile memory device

Methods, systems, and devices for techniques to improve latency for gaming applications are described. The memory system may be configured to operate in a gaming mode that may enable faster load times. In some cases, the gaming mode may enable faster game download from an external server. In some cases, the gaming mode may enable faster transferring of files between volatile storage and non-volatile storage at the memory system. The gaming mode may enable faster read and write operations, and faster switching between one or more gaming applications. The memory system may additionally or alternatively be configured to operate in a non-gaming mode which may improve reliability and retention for other, non-gaming applications. The memory system may switch between the two modes depending on an application being executed by the system.

Techniques to improve latency for gaming applications

Methods, systems, and devices for techniques for memory system refresh are described. In some cases, a memory system may prioritize refreshing blocks of memory cells containing control information for the file system of the memory system. For example, the memory system may identify a block of memory cells containing control information and adjust an error threshold for refreshing the blocks of memory cells to be lower than an error threshold for refreshing the blocks of memory cells containing data other than control information. Additionally or alternatively, the memory system may perform a refresh control operation for the block of memory cells with a higher frequency (e.g., more frequently) than for other blocks of memory cells.

Techniques for memory system refresh

A memory system having multiple address tables to translate logical addresses to physical addresses at different granularity levels is disclosed. For example, a first address table is associated with a first block size of translating logical addresses for accessing system files and application files; and a second address table is associated with a second block size of translating logical addresses for storing and/or retrieving data from an image sensor of a surveillance camera. A user interface can be used to access a configuration option to specify the second block size; and a user may indicate a typical size of an image or video file to be recorded by the surveillance camera to calculate the second block size and thus configure the second address table for a partition to record the image or video files.

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Shanghai, China

Qi Dong