Gyrfalcon Technology Inc.

Qi Dong

Lin Yang

Chyu-Jiuh Torng

Baohua Sun

Yongxiong Ren

Daniel H Liu

Yequn Zhang

A system may include multiple client devices and a processing device communicatively coupled to the client devices. Each client device includes an artificial intelligence (AI) chip and is configured to generate an AI model. The processing device may be configured to (i) receive a respective AI model and an associated performance value of the respective AI model from each of the plurality of client devices; (ii) determine an optimal AI model based on the performance values associated with the respective AI models from the plurality of client devices; and (iii) determine a global AI model based on the optimal AI model. The system may load the global AI model into an AI chip of a client device to cause the client device to perform an AI task based on the global AI model in the AI chip. The AI model may include a convolutional neural network.

Systems and methods for determining an artificial intelligence model in a communication system

A device for obtaining a local optimal AI model may include an artificial intelligence (AI) chip and a processing device configured to receive a first initial AI model from the host device. The device may load the initial AI model into the AI chip to determine a performance value of the AI model based on a dataset, and determine a probability that a current AI model should be replaced by the initial AI model. The device may determine, based on the probability, whether to replace the current AI model with the initial AI model. If it is determined that the current AI model be replaced, the device may replace the current AI model with the initial AI model. The device may repeat the above processes and obtain a final current AI model. The device may transmit the final current AI model to the host device.

An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

Method of self-testing and reusing of reference cells in a memory architecture

CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.

Memory subsystem in CNN based digital IC for artificial intelligence

CNN based digital IC for AI contains a number of CNN processing units. A first CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem, which includes a first one-time-programming (OTP) memory for filter coefficients and a second memory for imagery data. A second CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem that includes a first memory for filter coefficients, a second memory for imagery data and a third OTP memory for unique data pattern (e.g., security purpose). Either STT-RAM or OST-MRAM can be configured as different memories of the memory subsystem.

Buffer memory architecture for a CNN based processing unit and creation methods thereof

Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first embedded memory and second embedded memory. The first embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.

Embedded memory subsystems for a CNN based processing unit and methods of making

CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.

MLC based magnetic random access memory used in CNN based digital IC for AI

Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first memory and second memory. The first memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.

Fabrication methods of forming memory subsystem of CNN based digital IC for AI are disclosed. The method in SLC technology includes: providing a metal layer, forming a via layer, forming a HSL, forming a MTJ element layer and then etching out unmasked portions of the MTJ element layer to form at least two groups of different sized MTJ elements. The method in MLC technology includes: providing a metal layer, forming a via layer, forming a first HSL, forming a first MTJ element layer, etching out unmasked portions of the first MTJ element layer to form lower MTJ elements, forming a second HSL, forming a second MTJ element layer and etching out unmasked portions of the second MTJ element layer to form upper MTJ elements. Same sized first MTJ element layer and the second HSL are formed together.

Fabrication methods of memory subsystem used in CNN based digital IC for AI

Systems and methods for forming embedded memory in a processing unit. The methods include: depositing a dielectric layer on a metal landing pad of a logic circuit of a processing unit; opening vias in the dielectric layer; filling in the vias; performing chemical mechanical polishing (CMP); depositing an adhesion and topography planarization (ATP) layer; etching away portions of the ATP layer; filling in with inter layer dielectric (ILD) materials; performing CMP; depositing a MTJ film layer; patterning and etching away portions of the MTJ film layer; filling in with dielectric materials; performing CMP; and forming a bit line on the top layer. The methods may also include annealing in a forming gas during different steps of the above processed to reduce the high stress from the making of multi-metal layers of the processing unit at high temperature. This may prevent wafer warpage and/or significant topography in the fabrication process.

Process of fabricating embedded spin transfer torque memory for cellular neural network based processing unit

An integrated circuit processor having a processing unit that includes a logical circuit with multiple transistors and a top metal landing pad, and an embedded STT memory. The STT memory includes a dielectric layer formed on the top metal landing pad, an adhesion and topography planarization (ATP) layer formed on the dielectric layer, and an MTJ film layer disposed on the ATP layer. The memory may also include bit lines formed on the MTJ film layer. The ATP layer may have multiple layers such as a top layer and a bottom layer. The top layer may act as an etch stop for etching the MTJ film layer on the top. The ATP layer may have a total thickness of 500 A to 4000 A. The bit lines can be configured to send data to the logic circuit of the processing unit to perform one or more convolution neural network computations.

Growing community of inventors

San Jose, CA, United States of America

Qi Dong