Nitek, Inc.

Texas Instruments Corporation

Medical University of South Carolina

Sensor Electronic Technology, Inc.

Qhalid Fareed

Vinod Adivarahan

Asif Khan

Michael Shur

Remigijus Gaska

Asad Mahmood Haider

M Asif Khan

Grigory Simin

Naveen Tipirneni

Jungwoo Joh

Chang Soo Suh

Dong Seup Lee

Nicholas Stephen Dellas

Xuhong Hu

Sridhar Seetharaman

Tatsuya Tominari

Naveen Tipimeni

A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

P type gallium nitride conformal epitaxial structure over thick buffer layer

An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

Monolithic integration of high and low-side GaN FETs with screening back gating effect

A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Normally off III nitride transistor

A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a root mean square (rms) roughness of &#x3c;10 &#x212b; and (ii) a pit density for pits greater than (&#x3e;) 2 nm deep less than (&#x3c;) 10 pits per square &#x3bc;m with an average pit diameter less than (&#x3c;) 0.05 &#x3bc;m.

Method of fabricating non-etch gas cooled epitaxial stack for group IIIA-N devices

An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlGaN, where 0&#x3c;x&#x2264;1 having a thickness from about 10 &#x3bc;m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlGaN, where 0&#x3c;x&#x2264;1.

Ultraviolet light emitting devices and methods of fabrication

A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Buffer stack for group IIIA-N devices

Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.

Selectively area regrown III-nitride high electron mobility transistor

An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlGaN, where 0&#x3c;x&#x2266;1 having a thickness from about 10 &#x3bc;m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlGaN, where 0&#x3c;x&#x2266;1.

Utlraviolet light emitting devices and methods of fabrication

An improved process for forming a UV emitting diode is described. The process includes providing a substrate. A super-lattice is formed directly on the substrate at a temperature of at least 800 to no more than 1,300&#xb0; C. wherein the super-lattice comprises AlInGaN wherein 0&#x3c;x&#x2266;1, 0&#x2266;y&#x2266;1 and 0&#x3c;x+y&#x2266;1. A first conductive layer with a first type of conductivity is formed on the super-lattice wherein the first conductive layer comprises AlInGaN wherein 0&#x3c;x&#x2266;1, 0&#x2266;y&#x2266;1 and 0&#x3c;x+y&#x2266;1. A quantum well region is formed on the first conductive layer wherein the quantum well region comprises AlInGaN wherein 0&#x3c;x&#x2266;1, 0&#x2266;y&#x2266;1 and 0&#x3c;x+y&#x2266;1. A second conductive layer is formed on the quantum well with a second type of conductivity wherein the second conductive layer comprises AlInGaN wherein 0&#x3c;x&#x2266;1, 0&#x2266;y&#x2266;1 and 0&#x3c;x+y&#x2266;1. A first metal contact is formed in electrical contact with the first conductive layer and a second metal contact is formed in electrical contact with the second conductive layer.

High power ultraviolet light emitting diode with superlattice

Ultraviolet light emitting illuminator, and method for fabricating same, comprises an array of ultraviolet light emitting diodes and a first and second terminal. When an alternating current is applied across the first and second terminals and thus to each of the diodes, the illuminator emits ultraviolet light at a frequency corresponding to that of the alternating current. The illuminator includes a template with ultraviolet light emitting quantum wells, a first buffer layer with a first type of conductivity and a second buffer layer with a second type of conductivity, all deposited preferably over strain-relieving layer. A first and second metal contact are applied to the semiconductor layers having the first and second type of conductivity, respectively, to complete the LED. The emission spectrum ranges from 190 nm to 369 nm. The illuminator may be configured in various materials, geometries, sizes and designs.

Ultraviolet light emitting diode with AC voltage operation

Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.

Method to increase breakdown voltage of semiconductor devices

A vertically conducting LED comprising, in a layered arrangement: a highly thermally conductive submount wherein the highly conductive submount has a thermal conductivity of at least 100 W/mK; a p-type layer comprising AlInGaN wherein 0&#x2266;x&#x2266;1 and 0&#x2266;y&#x2266;1; a quantum well layer comprising AlInGaN wherein 0&#x2266;x&#x2266;1 and 0&#x2266;y&#x2266;1; an n-type layer comprising AlInGaN wherein 0&#x2266;x&#x2266;1 and 0&#x2266;y&#x2266;1; and an n-type contact layer wherein the LED has a peak emission at 200-365 nm.

Growing community of inventors

Columbia, SC, United States of America

Qhalid Fareed