Freescale Semiconductor,inc.

Nxp Usa, Inc.

Qadeer A Qureshi

Thomas Jew

Henning F Spruth

Reinaldo Silveira

John J Vaglica

Arnaldo R Cruz

Ryan D Bedwell

William C Moyer

Ravindraraj Ramaraju

James David Burnett

Alexander Hoefler

Christopher K Y Chun

Jack M Higman

Sushama Davar

Curtis F Wyman

Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.

Hardware-based memory initialization

A content addressable memory (CAM) and methods of operating a CAM are provided. The method for operating a CAM includes: during a first mode, performing a search function in a CAM bit array, the search result output at a match port of the CAM bit array; and during a second mode, columnwise reading data in the CAM bit array, the read column data output at the match data port of the CAM bit array. The method may include writing the CAM bit array with a predetermined data pattern. The method may further include providing an indication of pass/fail based upon comparing the read column data with expected data.

Content addressable memory with search line test circuitry

A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.

Memories having a built-in self-test (BIST) feature

A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.

Dynamic voltage adjustment for memory

A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.

Apparatus and method for adjusting an operating parameter of an integrated circuit

A memory not only uses redundant cells but also redundant references to reduce the likelihood of a failure. In one approach a failure in a reference can cause both the primary cell as well as the redundant cell to be ineffective. To overcome this potential problem two references for each bit are employed. In one form, the primary cell of a first bit is compared to one reference and the redundant cell of the first bit is compared to another reference. The primary and redundant cell of a second bit can use these two references as well. In another aspect, two references are placed in parallel for both the primary and redundant cell of the bit.

Memory with fault tolerant reference circuitry

Storage circuitry () may be used to store the values of fuses () so that storage circuitry () can be read instead of fuses (). By accessing the fuse values from storage circuitry () rather than from fuses (), there will be no sense current to fuses () that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry () thus significantly improves the reliability of fuse module (). For some embodiments, selection storage circuitry () may be used to determine whether storage circuitry () may be read or whether one of fuses () must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry () can also be used as direct hardware signals ().

Integrated circuit fuses having corresponding storage circuitry

A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.

Temperature based DRAM refresh

A non-volatile memory system () includes a magnetoresistive random access memory (MRAM) () including a plurality of magnetoresistive memory cells, a floating-gate nonvolatile memory () including a plurality of floating-gate memory cells, and a controller () coupled to the MRAM () and to the floating-gate nonvolatile memory (). The controller () is adapted to be coupled to a system bus () and controls a selected one of the MRAM () and the floating-gate nonvolatile memory () in response to an access initiated from the system bus ().

Nonvolatile memory system using magneto-resistive random access memory (MRAM)

Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

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Dripping Springs, TX, United States of America

Qadeer A Qureshi