Newport Fab, LLC

Conexant Systems, Inc.

Skyworks Solutions, Inc.

Q Z Liu

Bin Zhao

David J Howard

Maureen R Brongo

Phil N Sherman

David Feiler

Lawrence E Camilletti

Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor, is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

On-chip inductors

Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered, for example with photoresist, while a second area of the dielectric layer is exposed to a dielectric conversion source such as E-beams, I-beams, oxygen plasma, or an appropriate chemical. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of capacitor trenches are etched in the second area of the dielectric. The capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area. In another embodiment, the exposure to the dielectric conversion source is not performed until after the chemical mechanical polish has been performed. In yet another embodiment, a blanket layer of metal, such as aluminum, is first deposited. The blanket layer of metal is then etched to form metal lines. Then a gap fill dielectric is utilized to fill the gaps between the remaining metal lines. A first area of the gap fill dielectric is then covered and a second area of the gap fill dielectric is exposed to a dielectric conversion source. After exposure to the dielectric conversion source, the dielectric constant of the gap fill dielectric in the second area increases. The metal lines in the second area can then be used as capacitor electrodes of a high density capacitor.

Selective fabrication of high capacitance density areas in a low dielectric constant material

Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered while a second area of the dielectric layer is exposed to a dielectric conversion source. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of interconnect trenches are etched in the first area of the dielectric and a number of capacitor trenches are etched in the second area of the dielectric. The interconnect trenches and the capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area.

Method for selective fabrication of high capacitance density areas in a low dielectric constant material

In an exemplary embodiment of the disclosed transformer, the transformer comprises a dielectric area. For example, the dielectric area can consist of three different dielectric layers. Also, by way of example, the dielectric area can comprise silicon dioxide or a low-k dielectric. According to the exemplary embodiment, the dielectric area is interspersed with a permeability conversion material. The permeability conversion material has a permeability higher than the permeability of the dielectric area. For example, the permeability conversion material can be nickel, iron, nickel-iron alloy, or magnetic oxide. The exemplary embodiment further comprises a first conductor and also a second conductor patterned into the dielectric area. The first and/or the second conductor can comprise copper, aluminum, or a copper-aluminum alloy. Each of the first and second conductors are made up of a number of turns which result in, respectively, the primary and secondary windings of the exemplary disclosed transformer.

On-chip transformers

Fabrication of improved low-k dielectric structures is disclosed. Low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. In one embodiment, the physical properties of a low-k dielectric material is modified by exposing the low-k dielectric material to electron beams. The exposed portion of the low-k dielectric material becomes easier to etch and clean and exhibits greater mechanical strength and a reduction in absorption of moisture. In another embodiment, a number of incremental exposure and etch steps are performed to fabricate a desired structure. In yet another embodiment, the steps of exposure of a low-k dielectric material are combined with the etch steps. The exposure and the etching of the low-k dielectric material are performed concurrently in the same system. In still another embodiment, a single exposure and a single etch step are utilized to fabricate a desired structure. All the disclosed embodiments can be practiced by exposing the low-k dielectric material to ion beams instead of electron beams.

Fabrication of improved low-k dielectric structures

According to various embodiments, a conductor is patterned in a dielectric. The conductor can be patterned, for example, in the shape of a square spiral. The conductor can comprise, for example, copper, aluminum, or copper-aluminum alloy. The dielectric can be, for example, silicon oxide or a low-k dielectric. Trenches are etched next to the patterned conductor in the dielectric. The trenches are filled with a material having a permeability substantially higher than the permeability of the dielectric. The high permeability material can be, for example, nickel, iron, nickel-iron alloy, or magnetic oxide. As a result, an inductor having a high inductance value is achieved without lowering the quality factor of the inductor.

Method for fabrication of high inductance inductors and related structure

According to various disclosed embodiments, a conductor is patterned in a dielectric. The conductor can be patterned, for example, in the shape of a square spiral. The conductor can comprise, for example, copper, aluminum, or copper-aluminum alloy. The dielectric can be, for example, silicon oxide or a low-k dielectric. A spin-on matrix containing high permeability particles is then deposited adjacent to the patterned conductor. The high permeability particles comprise material having a permeability substantially higher than the permeability of the dielectric. The high permeability particles can comprise, for example, nickel, iron, nickel-iron alloy, or magnetic oxide. As a result, an inductor having a high inductance value is achieved without lowering the quality factor of the inductor.

Method for fabricating on-chip inductors and related structure

Method for fabrication of damascene interconnects and related structures is disclosed. A sacrificial layer is formed over a low-k dielectric. Trenches are then etched inside the sacrificial layer and the low-k dielectric. The trenches are then filled with metal. During a first CMP process, excess metal over the sacrificial layer is removed. During a second CMP process, the sacrificial layer over the low-k dielectric and any remaining excess metal are removed. By the end of the second CMP process substantially all of the sacrificial layer and all of the excess metal are removed. In this manner, the trenches in the low-k dielectric are filled with metal where the metal surface is substantially flush with the surface of the low-k dielectric.

Method for fabrication of damascene interconnects and related structures

Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

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Irvine, CA, United States of America

Q Z Liu