Arm Limited

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Seow Chuan Lim

Zhuoran Wang

Gergely Tóth

Péter Vári

Barnabás Sipos

Dezso Imre Novak

A direct memory access (DMA) controller comprises template storage circuitry to store at least one DMA template indicative of a DMA data access pattern. Each DMA template comprises enable indications settable to an enable state or a disable state. In response to a DMA command associated with a source address, a destination address, a source DMA template, and a destination DMA template, DMA control circuitry generates a set of DMA memory access requests to copy data from source memory system locations to destination memory system locations. The source/destination memory system locations are selected to have addresses which are offset relative to the source/destination address by offset amounts corresponding to positions of enable indications set to the enable state within the source/destination DMA template. The source/destination DMA templates allow irregular patterns of DMA accesses to be controlled in fewer DMA commands.

Direct memory access (DMA) controller issues memory access requests whereas memory locations having addresses which are offset amounts relative to destination template address

An apparatus and method are provided for filtering transactions performed between a master device and a slave device, where each transaction comprises one or more transfers. The apparatus has a first interface for coupling to the master device and a second interface for coupling to the slave device. Routing circuitry is used to route, between the first interface and the second interface, signals representing each transfer. Filtering decision generation circuitry is arranged to perform a combinatorial operation to generate a filtering decision dependent on current values of one or more received input variables. The routing circuitry is then responsive to the filtering decision indicating a block condition for a current transfer, to block the current transfer by preventing one or more of the signals representing that current transfer from being passed between the first interface and the second interface in either direction. The filtering decision generation circuitry is responsive to assertion of the current transfer within the apparatus to generate the filtering decision, and thereafter to maintain that filtering decision for a duration of time that the current transfer is asserted, irrespective of a change in the values of the input variables. Such an approach provides a high performance solution while also enabling certain bus protocol violation scenarios to be avoided.

Apparatus and method for filtering transactions

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Pilisvorosvar, Hungary

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