Samsung Electronics Co., Ltd.

Furex Co., Ltd.

Pyoung-Wan Kim

Chul-Yong Jang

Eun-Chul Ahn

Teak-Hoon Lee

Teak-hoon Lee

Jong-Ho Lee

Nam-seog Kim

Chul-yong Jang

Woon-bae Kim

Mitsuo Umemoto

In-Ku Kang

Hyeon Deuk Hwang

Kyoung-sei Choi

Seung-Kon Mok

Yung-cheol Kong

Tae-Sung Yoon

Min-Seung Yoon

Byoung-rim Seo

Kyong-soon Cho

Keum-hee Ma

Min-Ho O

Yoon-young Choi

Taek-Hoon Lee

Chang-soo Jin

Tae-weon Suh

Jung-Seok Ryu

Provided is a body-implantable package for processing biosensed-data for wireless communication to an external device. The package includes a tube closed by a cover, therein, a chip with a strained layer affixed thereto to form a flexible laminar circuit. The cover is fitted over an open end of the tube after the laminated chip and strained layer are inserted therein. The chip is constructed of and rolled in one or more turns into a generally cylindrical shape. The strained layer is affixed to a surface of the chip automatically to cause the flexible laminar circuit to curl into a generally cylindrical shape to fit within the tube.

Package for processing sensed-data, sensed-data processor, and system for processing sensed-data

Provided is an image sensor package that includes a transparent protection cover for protecting a plurality of unit pixels each including a microlens. The image sensor package includes a substrate which has a first surface and a second surface that are opposite to each other, and includes a sensor array region including a plurality of unit pixels formed in the first surface and a pad region including a pad arranged in the vicinity of the sensor array region, a plurality of microlenses formed on the plurality of unit pixels, respectively, at least two transparent material layers covering the plurality of microlenses, and a transparent protection cover attached onto the plurality of microlenses with the at least two transparent material layers interposed therebetween.

Image sensor package

In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

Semiconductor package having buried post in encapsulant and method of manufacturing the same

Provided is a chip stack package and a method of manufacturing the same. A chip stack package may include a base chip including a base substrate, a base through via electrode penetrating the base substrate, a base chip pad connected to the base through via electrode, and a base encapsulant. The chip stack package may further include at least one stack chip on a surface of the base substrate. The chip stack package may also include an external connection terminal connected to the base through via electrode and the base chip pad and protruding from the base encapsulant, and an external encapsulant surrounding and protecting outer surfaces of the base chip and the at least one stack chip, wherein the chip through via electrode and the chip pad are connected to the base through via electrode and the base chip pad of the base chip.

Chip stack package and method of fabricating the same

A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

Semiconductor package and electronic device having the same

A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.

Semiconductor package and methods of manufacturing the semiconductor package

A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Semiconductor chip package, electronic device including the semiconductor chip package and methods of fabricating the electronic device

In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.

Semiconductor package having resin substrate with recess and method of fabricating the same

A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs.

Semiconductor packages and methods of fabricating the same

A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate.

Semiconductor package using chip-embedded interposer substrate

A chip stack package may include a package substrate, a plurality of semiconductor chips mounted on the package substrate, bonding wires electrically connecting the semiconductor chips to the package substrate, and spacers interposed between the adjacent semiconductor chips. Each of the spacers may include a plurality of metal bumps. The spacers may be higher than the highest point of the bonding wire from the active surface of the semiconductor chip.

Chip stack package and manufacturing method thereof

A package substrate may have an improved surface structure for controlling the flow of an adhesive. The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be provided on the lower surface, clear of the passivation layer. The semiconductor package may have an indented or non-planar surface structure.

Package substrate and semiconductor package using the same

A method for manufacturing semiconductor devices is provided in which an organic adhesive layer is formed on the backside of a semiconductor wafer after being thinned by a backlapping process and cured to form a B-stage adhesive layer. Using the B-stage adhesive layer, the semiconductor device may then be attached to a circuit substrate and then subjected to additional curing to form a C-stage adhesive layer. Such semiconductor devices may also be attached directly to a lower semiconductor chip or, in the alternative, may be attached to a spacer mounted that is or will be mounted on a lower semiconductor chip or the circuit substrate. The organic adhesive is selected to counteract stresses induced by a passivation layer formed on the active surface, thereby reducing or preventing warping of the semiconductor wafer and eliminating the need for a separate resin paste adhesive during the chip attaching process.

Growing community of inventors

Suwon-si, South Korea

Pyoung-Wan Kim