Texas Instruments Corporation

Puvvada Venugopal

Charvaka Duvvury

Michael D Chaine

Sridhar Ramaswamy

Snehamay Sinha

Guru Chakrapani Prasad

C S Raghu

Gopalaro Kadamati

The invention comprises a semiconductor device with protection circuitry and a method of protecting an integrated circuit from electrostatic discharge. One aspect of the invention is a semiconductor device with protection circuitry which comprises an integrated circuit having at least one bond pad. A protection circuit is electrically connected to the bond pad and is operable to prevent damage to the integrated circuit during an electrostatic discharge event. The protection circuit comprises a first MOSFET having a first gate electrode connected in series with a second MOSFET having a second gate electrode wherein the first gate electrode and second gate electrode are commonly controlled in response to an electrostatic discharge event.

Semiconductor device with protection circuitry and method

For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.

Integrated circuit design error detector for electrostatic discharge and latch-up applications

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Bengaluru, India

Puvvada Venugopal