Xilinx, Inc.

Pushpasheel Tawade

Neil G Jacobson

Sanjay Srivastava

Bin Dai

Sungnien Jerry Mao

Emigdio M Flores, Jr

Rosa M Y Chow

Arthur H Khu

Conrad A Theron

Brian D Erickson

Farshid Shokouhi

Bernardo A Elayda, Iii

David E Schweigler

Methods and apparatus are disclosed for identifying a system. In various embodiments, values of identification codes are read from each of a plurality of electronic devices of the system. The values of the identification codes are used to generate a system identifier value.

Identification of multi-device systems

Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an order in a configuration chain of configurable devices in the system and identify configuration data sets associated with the configurable devices. A system identifier value is generated and associated with the chain description data set. An archive is generated including the configuration data sets, chain description data set, and system identifier value.

Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems

Method and system for a programmable device programmer. The disclosure describes various embodiments for programming a target programmable device by a programmer. In one embodiment, the programmer determines availability of updated configuration data for a hardware component of the programmer. The programmer includes the software component coupled to the hardware component. An update mode of the hardware component is enabled in response to availability of the updated configuration data, and programming of the target programmable device is disabled while the hardware component is in the update mode. A programmable device internal to the hardware component is programmed with the updated configuration data while the hardware component is in the update mode, and the update mode is disabled in response to completion of programming of the at least one programmable device. A target programmable device may then be programmed by the programmer having the updated configuration data.

Transmitting configuration data to a target programmable device after updating an intermediate programmable device

A bitstream having a plurality of data sets is provided to an integrated circuit device such as an FPGA having test circuitry capable of routing data to the device's internal resources, with each data set including configuration information and a trigger signal. Successive data sets of the bitstream are sequentially processed by the test circuitry in response to the trigger signals to sequentially initialize the device's resources to various states. For some embodiments, each data set includes configuration data to configure one or more configurable elements of the device to implement a desired design and includes soft data for use by a processor embedded within the device. For one embodiment, control logic is provided to selectively wait for a predetermined time period before processing a next data set.

Integrated data download

Various approaches for converting configuration data for programmable circuits are disclosed. In one embodiment, a first configuration bitstream is provided. The first configuration bitstream has a format compatible with a first protocol for communicating with and configuring the programmable circuit. A second protocol is selected for communicating with and configuring the programmable circuit, and the first configuration bitstream is converted to a second configuration bitstream. The second configuration bitstream has a format compatible with the second protocol. The programmable circuit is configured with the second configuration bitstream.

Conversion of configuration data to match communication protocol

According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data to go through the boundary scan register chain of the JTAG-compliant chip. This controller is used to program, erase, and read the other chip. For a non-JTAG flash memory device, the controller in the JTAG-compliant chip generates the necessary programming signal sequences, and applies them to the non-JTAG chip without going through the JTAG boundary scan circuitry.

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San Jose, CA, United States of America

Pushpasheel Tawade