Other

Pushkar U Mokashi

Edward Butler

Robert Tamlyn

Hemen R Shah

Alfred L Sartwell

Martin B Lundberg

An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n.sup.th bits of the SAM data.

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Lewisville, TX, United States of America

Pushkar U Mokashi