Transwitch Corporation

Pushkal Yadav

William G Bartholomay

Santanu Bhattacharya

Balaraj Vishnu Varthanan

Ashis Maitra

Sachin Mathur

Kumar Shakti Singh

Chitra Wadhwa

Yudhishthira Kundu

Diljit Singh

Amandeep Singh Gujral

Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.

Time multiplexed SONET line processing

An apparatus for handling back-to-back maintenance messages in extended superframe t telephone circuits includes a FIFO, a byte counter, and a message length register. According toga method of the invention, when messages are placed in the. FIFO, the byte counter counts the message length and places the message length in the message length register. A host controller is required to read the message length register in the time interval following complete receipt of a first message before complete receipt of a second message, but is only required to read the contents of the FIFO before it overflows. According to a presently preferred embodiment of the apparatus, a second register is provided for indicating the current depth of the FIFO. The second register sends an interrupt to the host controller when the contents of the FIFO exceed a threshold.

Methods and apparatus for handling maintenance messages in extended superframe T1 telephone circuits

A method and apparatus for reliably detecting both AIS and AIS-CI signals in the presence of a bit error ratio up to 1&times;10 includes an AIS detector having an AIS indication output, a CI detector having a CI indication output, and a two signal AND gate having its inputs coupled to the respective outputs of the detectors and having an output indicative of an AIS-CI detection. The AIS detector has an adjustable zero threshold and the CI detector has a threshold output coupled to the AIS detector for adjusting the zero threshold. According to the method of the invention, the AIS detector zero threshold is normally set at the normal threshold (1&times;10 ) but is reset to a higher threshold (e.g., 2&times;10 ) when the CI detector detects the presence of the CI code word. The AIS signal is detected in a normal way and the AIS-CI signal is detected only when the CI detector detects the presence of the CI code word AND the AIS detector detects the presence of the AIS signal using the higher zero threshold. According to a preferred embodiment, the zero threshold is raised if the CI detector detects two consecutive CI code words, but the CI indication output is indicated only of the CI detector detects eight CI code words in 40 ms. The zero threshold is returned to normal when the CI detector detects ten consecutive absences of the CI code word.

Alarm indication signal detection in the presence of special line codes in DS1 (T1) telephone circuits

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New Delhi, India

Pushkal Yadav