Cypress Semiconductor Corporation

Purushothaman Ramakrishnan

Shiva P Gowni

Rakesh Mehrotra

Pattikad Narayanan Ravindran

Chirakkal Varriam Unnikrishnan

Padma Nagaraja

A method of full semiconductor chip timing closure includes the steps of determining a system level place and route. Next, a static timing analysis for each of a number of subsystems is performed. Finally, a full chip static timing analysis is performed.

Method of full semiconductor chip timing closure

An apparatus configured to store and present data. The apparatus may comprise a plurality of storage elements configured to store one or more wordline signals. Each of the plurality of storage elements may be implemented within a memory cell.

Deep pipe synchronous SRAM

A circuit comprising a memory array, a driver circuit, and a logic circuit. The memory array may have a plurality of memory cells arranged in a plurality of rows. Each cell may be configured to read and write data. The driver circuit may be configured to present a plurality of word line signals in response to a decoded row signal and a disable signal. The logic circuit may be configured to generate the disable signal in response to (i) one or more programmed redundant row signals and (ii) a decoded group signal.

Row redundancy scheme

The output (3) of a level shifter (1) is split into two paths (4,5) with a delay (.tau..sub.1, .tau..sub.2) being introduced into at least one path to enable rise delay and fall delay to be controlled independently of one another. In the context of an integrated circuit which includes a memory device, the use of an additional path allows control of the set-up and hold times in that one transition can be speeded up or slowed down independently of the other transition to achieve the best possible set-up and hold times.

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Bengaluru, India

Purushothaman Ramakrishnan