Hewlett-Packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Purna C Murthy

Mark J Thompson

Michael Lawrence Sabotta

Sohail Hameed

Thomas W Grieff

A system and related method for calculating parity information for disk array drive failure recovery. More specifically, using eight bit coefficients and calculating parity information using valid eight bit encryption keys to produce finite field encrypted resultant multiplication. Further disclosed is a method of determining whether a potential encryption key of a particular number of bits produces valid results for all possible multiplications in determining parity values.

Encryption keys for multiple drive fault tolerance

A system and method is disclosed for debugging of a hardware board that includes a processor with only a single level of interrupts that are either all enabled or all disabled. The processor does not implement nonmaskable interrupts. The processor on the board contains a machine check exception (MCP) input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the hardware board. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the interrupt processor are disabled. A processor-to-bus bridge connected to the processor on the hardware board contains a critical interrupt register. Test equipment connected to the processor-to-bus bridge sets a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo interrupt debug request has occurred. The processor-to-bus bridge asserts the MCP input line of the processor after determining that the test equipment has requested the nonmaskable pseudo-interrupt. The processor then executes handler software that communicates with the test equipment to debug the hardware board.

Nonmaskable interrupt workaround for a single exception interrupt handler processor

A method and related system for generating error correction or parity information in a multiple disk computer system supporting multiple drive fault tolerance. The method involves defining parity equations to be based not only on data written to drives of the computer system but also on other parity information such that in solving for missing data, specific equations need not be used. Defining parity equations in this manner, in combination with a coefficient matrix that defines the coefficients of the various parity equations, ensures the ability to solve for the missing data even if some of the failed drives contain parity information.

Multiple drive failure recovery for a computer system having an array of storage drives

A computer system with an array of disk drives is disclosed. The drive array is capable of supporting greater than 15 drive fault tolerance accomplished by using coefficients for parity equations spanning greater than eight bits.

Computer system with greater than fifteen drive fault tolerance

In a computer system there is a storage subsystem and an array controller circuit controlling an array of hard drives in the storage subsystem. Upon powering the storage subsystem, the array controller automatically determines whether the hard drives have been moved to new bay locations in the storage subsystem and whether a new complete logical drive, consisting of at least one hard drive, has been added to the storage subsystem. Upon discovery of any drive movement or logical drive unit addition, the array controller automatically reconfigures each hard drive by at least updating the configuration information in accordance with the changes.

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Houston, TX, United States of America

Purna C Murthy