Vmware, Inc.

Puneet Zaroo

Carl Alan Waldspurger

Rajesh Venkatasubramanian

Richard West

Xiao Zhang

Haoqiang Zheng

Alexander T Garthwaite

Ganesha Shanmuganathan

Mustafa Uysal

Xiaoyun Zhu

Aashish Parikh

Yury Baskakov

Sahan Bamunavita Gamage

Kalyan Saladi

Seongbeom Kim

Madhuri Yechuri

Sachin Manpathak

Luis Useche

Alexandre Milouchev

Ricardo Koller

A management server and method for performing resource management operations in a distributed computer system takes into account information regarding multi-processor memory architectures of host computers of the distributed computer system, including information regarding Non-Uniform Memory Access (NUMA) architectures of at least some of the host computers, to make a placement recommendation to place a client in one of the host computers.

NUMA-based client placement

Systems and methods for performing selection of non-uniform memory access (NUMA) nodes for mapping of virtual central processing unit (vCPU) operations to physical processors are provided. A CPU scheduler evaluates the latency between various candidate processors and the memory associated with the vCPU, and the size of the working set of the associated memory, and the vCPU scheduler selects an optimal processor for execution of a vCPU based on the expected memory access latency and the characteristics of the vCPU and the processors. The systems and methods further provide for monitoring system characteristics and rescheduling the vCPUs when other placements provide improved performance and efficiency.

Adaptive CPU NUMA scheduling

A management server and method for performing resource management operations in a distributed computer system utilizes interference scores for clients executing different workloads to create an interference affinity-type rule for at least some of the clients contending for a resource based on the interference scores for that resource. The interference affinity-type rule can then be used to recommend a target host computer to place a client.

Interference-aware client placement

A management server and method for performing resource management operations in a distributed computer system utilizes interference scores for clients executing different workloads, including a client to be placed in the distributed computer system, as utilization values of resources, which are assigned continuously variable weights to produce weighted resource utilization values. The weighted resource utilization values are used to generate overall selection scores for host computers of the distributed compute system, which are then used to recommend a target host computer among the host computers of the distributed computer system to place the client.

Interference-based client placement using dynamic weights

In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.

NUMA scheduling using inter-VCPU memory access estimation

Exemplary methods, apparatuses, and systems determine a miss-rate at various amounts of memory allocation for each of a plurality of workloads running within a computer. A value representing an estimated change in miss-rate for each of the workloads based upon an increase in a current allocation of memory to the workload is determined. The workload with a value representing a greatest improvement in hit rate is selected. Additional memory is allocated to the selected workload.

Data reuse tracking and memory allocation management

NUMA scheduling using inter-vCPU memory access estimation

A method includes assigning a thread performance counter to threads being created in the computing environment, the thread performance counter measuring a number of cache misses for a corresponding thread. The method also includes calculating a self-thread value S as a change in the thread performance counter of a given thread during a predetermined period, calculating an other-thread value O as a sum of changes in all the thread performance counters during the predetermined period minus S, and calculating an estimation adjustment value associated with a first probability that a second set of cache misses for the corresponding thread replace a cache area currently occupied by the corresponding thread. The method also includes estimating a cache occupancy for the thread based on a previous occupancy for the thread, S, O, and the estimation adjustment value, and assigning computing environment resources to the thread based on the estimated cache occupancy.

Cache performance prediction and scheduling on commodity processors with shared caches

A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.

Thread scheduling based on predicted cache occupancies of co-running threads

Methods, computer programs, and systems for managing thread performance in a computing environment based on cache occupancy are provided. In one embodiment, a computer implemented method assigns a thread performance counter to threads being created to measure the number of cache misses for the threads. The thread performance counter is deduced in one embodiment based on performance counters associated with each core in a processor. The method further calculates a self-thread value as the change in the thread performance counter of a given thread during a predetermined period, and an other-thread value as the sum of all the changes in the thread performance counters for all threads except for the given thread. Further, the method estimates a cache occupancy for the given thread based on a previous occupancy for the given thread, and the calculated shelf-thread and other-thread values. The estimated cache occupancy is used to assign computing environment resources to the given thread. In another embodiment, cache miss-rate curves are constructed for a thread to help analyze performance tradeoffs when changing cache allocations of the threads in the system.

Online computation of cache occupancy and performance

Exemplary methods, apparatuses, and systems receive a first request for a storage address at a first access time. Entries are added to first and second data structures. Each entry includes the storage address and the first access time. The first data structure is sorted in an order of storage addresses. The second data structure is sorted in an order of access times. A second request for the storage address is received at a second access time. The first access time is determined by looking up the entry in first data structure using the storage address received in the second request. The entry in the second data structure is looked up using the determined first access time. A number of entries in second data structure that were subsequent to the second entry is determined. A hit count for a reuse distance corresponding to the determined number of entries is incremented.

A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level cache (LLC), and a main memory. In one embodiment, at each descheduling event of the thread following an execution interval, an effective CPU time is determined. The execution interval is a period of time during which the thread is being executed on the central processing unit (CPU) between scheduling events. The effective CPU time is a portion of the execution interval that excludes delays caused by contention for microarchitectural resources, such as time spent repopulating lines from the LLC that were evicted by other threads. The thread may be compensated for microarchitectural contention by increasing its scheduling priority based on the effective CPU time.

Compensating threads for microarchitectural resource contentions by prioritizing scheduling and execution

Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.

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Santa Clara, CA, United States of America

Puneet Zaroo