Qualcomm Incorporated

Puneet Talwar

Suresh Kumar Venkumahanti

Stephen Robert Shannon

Karan Suri

Sharing loop cache instances among multiple threads in processor devices is disclosed herein. In some aspects, a processor device provides a loop cache controller circuit that is configured to detect a first iteration of a loop body, comprising a plurality of loop instructions, in an instruction stream executed by a first thread. The loop cache controller circuit determines that the loop instructions were previously stored in a loop cache instance associated with a second thread, and, in response, sets a use bit corresponding to the first thread of a use bit register corresponding to the loop cache instance. Upon detecting a subsequent iteration of the loop body by the first thread, the loop cache controller circuit retrieves the plurality of loop instructions from the loop cache instance instead of an instruction cache, based on the use bit corresponding to the first thread.

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Austin, TX, United States of America

Puneet Talwar