Texas Instruments Corporation

Puneet Sabbarwal

Indu Prathapan

Pankaj Gupta

Prakash Narayanan

Rubin Ajit Parekhji

Aishwarya Dubey

Rajesh Kumar Mittal

Anand Bhat

Naishad Parikh

Pranjal Tiwari

An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.

Bitonic sorting accelerator

In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.

Save-restore in integrated circuits

Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.

Integrated circuits capable of generating test mode control signals for scan tests

A scannable storage circuit includes a scan enable input, a storage element having a Node coupled to a data output buffer for driving a data output terminal. The data output buffer includes an inverter; a transmission gate having a first MOS transistor and a second MOS transistor with sources and drains coupled to each other, drains coupled to an output of the inverter and sources coupled to the data output terminal and gates coupled to the scan enable input and an inverted scan enable input. A third MOS transistor and a fourth MOS transistor is coupled to the sources of the first and second MOS transistors, the third MOS transistor and fourth MOS transistor are configured to pull up or pull down the data output terminal in response to a first control signal and a second control signal respectively. A scan output is generated from the output of the inverter.

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Bengaluru, India

Puneet Sabbarwal