Cadence Design Systems, Inc.

Hewlett-packard Development Company, L.p.

Other

Emc IP Holding Company LLC

Puneet Kumar Arora

Steven Lee Gregor

Norman Robert Card

Navneet Kaushik

Krishna Chakravadhanula

Diane R Hammerstad

Brian Edward Foutz

Kumaravel Ganesan

Shinoj Bhaskaran

Christos Papameletis

Sarthak Singhal

Ruby Tomar

Subhasish Mukherjee

Ankit Bandejia

Hung The Dinh

Vivek Chickermane

Ritesh Ranjan Jha

Sabu K Syed

Patrick Gallagher

Rajesh Krishnan

Manikandan Pammal Rathinavelu

Vijaykumar Nayak

Seshadri Srinivasan

Vijaya Panguluru Sekhar

Kiran Kumar Pidugu

Geetha Venkatesan

Sourav Datta

Muhammed Mohiuddin

Mohit Madaan

Lakshman Kumar Tiwari

Ranjani Muthyam Venkata

Ke Zhang

Dhanendra Jain

Gurpreet Singh Bhatia

Hanumantha Raya

A memory view generator evaluates a module design file characterizing a memory module to generate a set of port functions that defines operations of ports on a memory module for a memory view file. The memory view generator parses a memory module bitmap characterizing a physical layout of the memory module to determine a physical memory model of address bits, an order of rows, an order of columns, an order of banks and data bits of the memory module for the physical memory view file. A circuit simulator instantiates a memory module and provide simulation results based on a simulation memory model of the memory module, the set of port functions and the physical memory model. The memory view generator analyzes the simulation results to determine operational performance characteristics of the memory module for the memory view file.

Memory view for memory module

Embodiments included herein are directed towards a launch off shift circuit module. Embodiments included a first flip-flop configured to receive a clock signal and a scan enable signal. Embodiments may further include a combinational logic circuit configured to receive an input from the first flip-flop and a launch off shift mode signal. The first flip-flop and the combinational logic circuit may be located inside a launch off shift module boundary.

Launch off shift process

This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

Systems and methods for scan chain stitching

A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.

Memory view for non-volatile memory module

An NVM algorithm generator that evaluates a Liberty file characterizing an NVM module and a memory view of the NVM module that identifies ports and associated operations of the NVM module to generate a control algorithm. The control algorithm includes a read algorithm that includes an order of operations for assigning values to ports of the NVM module to assert a read condition of a strobe port, executing a memory read on the NVM module and setting values to the ports on the NVM module to assert a complement of a program condition. The control algorithm also includes a program algorithm that includes an order of operations for assigning values to ports of the NVM module to assert the program condition of the strobe port, executing a memory write and setting values to the ports on the NVM module to assert the complement of the program condition.

Control algorithm generator for non-volatile memory module

Methods, apparatus, and processor-readable storage media for transaction visibility framework implemented using artificial intelligence are provided herein. An example computer-implemented method includes monitoring data related to a transaction flow across multiple layers of an enterprise system; determining which of the multiple layers correspond to at least one detected problem within the transaction flow by applying artificial intelligence techniques to the data; generating a visualization of the transaction flow, wherein generating the visualization comprises generating a sequential view of the transaction flow, generating one or more parallel sub-transaction flows pertaining to one or more dependencies of the transaction flow, and producing a visual indication of the detected problem; determining, based on analyzing the generated visualization, one or more automated actions related to the detected problem and the determined layer of the enterprise system corresponding to the detected problem; and automatically initiating the one or more automated actions.

Transaction visibility frameworks implemented using artificial intelligence

An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.

Simulation event reduction and power control during MBIST through clock tree management

Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test ('MBIST'). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.

Failing read count diagnostics for memory built-in self-test

An exemplary fuse control arrangement can be provided, which can include, for example, a fuse control unit(s), which includes a test access method interface(s) and a programmable memory(ies), wherein the fuse control unit(s) is configured to provide fuse information to repair a memory(ies). The fuse control unit(s) can be coupled to the memory(ies) and the memory(ies) can be coupled to a register repair unit(s). The fuse control unit(s) can provide the register repair unit(s) with the fuse information to repair the memory(ies).

Multiple-channel, programmable fuse control unit

Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test ('MBIST'). Embodiments provide for a two-pass diagnostic test of the target memory, wherein, in the first pass, a data compare unit provides clock cycle values associated with detected mis-compares to a tester, and, in the second pass, the data compare unit extracts data vectors associated with the clock cycle values. Embodiments further provide for a bit fail map report that is generated based on the extracted data vectors.

Dynamic diagnostics analysis for memory built-in self-test

An exemplary system, method, and computer-accessible medium for modifying a memory unit(s) may be provided, which may include, for example, determining a location of a first memory built-in self-test (MBIST) logic(s) in the memory unit(s), removing the first MBIST logic(s) from the memory unit(s), and inserting a second MBIST logic(s) into the memory unit(s) at the location. The second MBIST logic(s) may be based on the first MBIST logic(s). The second MBIST logic(s) may be generated, which may be performed by modifying the first MBIST logic(s). The first MBIST logic(s) may be modified based on a modification(s) to a register transfer level (RTL) list associated with the memory unit(s). A pattern control file or a Test Data Register mapping file may be modified based on the modification to the first MBIST logic(s).

Register-transfer level design engineering change order strategy

Computer system for programmable built-in self-test (PMBIST) insertion into system-on-chip designs comprising one or more memories, including at least one processor and computer-executable instructions that cause the system to determine a PMBIST configuration based on one or more test configuration files; generate one or more package files based on the PMBIST configuration; insert PMBIST hardware into the SoC design based on the package files and characteristics of the memories; suspend PMBIST hardware insertion after an event related to the package files; and resume PMBIST hardware insertion after receiving one or more updated package files. In some embodiments, the package files are independent of vendor-specific memory models. In some embodiments, the package files comprise a plurality of data structures. Exemplary methods and computer-readable media can also be provided embodying one or more procedures the system is configured to perform.

Systems, methods, and computer-readable media utilizing improved data structures and design flow for programmable memory built-in self-test (PMBIST)

An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group ('JTAG') controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).

Customizable built-in self-test testplans for memory units

Examples disclosed herein relate to wireless communication of print content. Examples include a remote printing request acquired by a remote printing server from a mobile device, the remote printing request including first print content and identifying a mobile device identifier. Examples further include second print content and the mobile device identifier acquired via direct wireless communication.

Wireless communication of print content and a mobile device identifier

Electronic design automation (EDA) systems, methods, and computer readable media are presented for adding design for test (DFT) logic at register transfer level (RTL) into an integrated circuit (IC) design at RTL. In some embodiments, the DFT logic at RTL includes a port that connects to a hierarchical reference with a hierarchical path in the tree structure hierarchy to a part of the IC design at RTL. Such DFT modification helps to decrease the number of new ports added at this stage, and as a result assists subsequent debugging and back-annotation of RTL.

Growing community of inventors

Delhi, India

Puneet Kumar Arora