Apple Inc.

Google Inc.

Compaq Computer Corporation, Inc.

P.a. Semi, Inc.

Puneet Kumar

Mark Hayter

Po-Yung Chang

Sudarshan Kadambi

Michael J Smith

Josh P De Cesare

Ruchi Wadhawan

Bernard Joseph Semeria

Dominic Go

Choon Ping Chng

Andrew David Birrell

Christopher Thomas Lyon

Rachel Nancollas

Willis Calkins

Duncan Laurie

William Laing

Michael Smith

A computing system is configured to securely boot different operating systems. The computing system includes one or more processors, a first memory device storing a first firmware element for booting a first operating system, a second memory device storing a second firmware element for booting a second operating system, a first security module configured to provide authentication for booting the first operating system, and a second security module configured to provide authentication for booting the second operating system. The computing system is configured such that, when the first security module is connected to the one or more processors, either the first operating system or the second operating system is selected for booting based on a selection signal, and when the first security module is not connected to the one or more processors, the second operating system is selected for booting.

Enabling multiple secure boot paths on a hardware platform

In one general aspect, a method can include receiving, by a computing device, an indication of movement of the computing device, receiving, by the computing device, an input from one of a touchpad, a touch-sensitive surface of a lid portion of the computing device, a trackpad, one or more mouse buttons, and a keyboard during the movement of the computing device, determining, based on the received indication of the movement of the computing device, that the received input is a false input, and ignoring, by the computing device, the received input based on determining that the received input is a false input.

Selective override of touch display inputs

In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

Power managed lock optimization

In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

Data flow control within and between DMA channels

In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache. In an embodiment, the prefetch unit is configured to check for a cache hit for a prefetch request by checking a duplicate cache tags.

Data prefetch unit utilizing duplicate cache tags

In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

Prefetch unit

A portable audio player stores a large amount of compressed audio data on an internal disk drive, and loads a portion of this into an internal random access memory (RAM) which requires less power and less time to access. The audio player plays the data stored in RAM and monitors the amount of unplayed data. When the amount of unplayed data falls below a threshold, additional data is copied from the disk drive into RAM. Because the time necessary to copy a block of data from the disk drive to RAM is much less than the amount of time it takes to play the same block of audio data from RAM, this approach minimizes the amount of time that the disk drive must be operated, and thus minimizes the amount of power consumed by the system.

Low power system and method for playing compressed audio data

Growing community of inventors

Mountain View, CA, United States of America

Puneet Kumar