Nvidia Corporation

Intel Corporation

Amazon Technologies, Inc.

Puneet Gupta

Ilyas Elkin

Wojciech Jakub Poppe

David T Wang

Xin Li

Amit D Sanghani

Sreejit Chakravarty

Vidhyananth Ramasamy Venkatasamy

Fei Su

Anubhav Sinha

Thomas Gang Wang

Rakesh Reddy Kandula

Terrence Huat Hin Tan

Wei Ming Lim

Sudheer V Badana

Adithya B S

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

Test architecture for die to die interconnect for three dimensional integrated circuits

A modular recharging system includes an electronic device that performs diagnostics on a removable battery pack that the electronic device can use to boost the power of its internal battery. Typically, the battery pack will have a larger battery than the internal battery of the device. The electronic device determines whether the battery pack will take a charge before determining whether the battery pack is authorized to assure that an authorization failure is not due to other issues such as a dead battery, an underpowered battery, or a broken connection between devices.

Smart diagnostics for hot-pluggable battery systems

Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.

Via resistance analysis systems and methods

The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominant impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominant characteristic oscillating rings, wherein each respective one of the plurality of dominant characteristic oscillating rings includes a respective dominant characteristic. Additional analysis can be performed correlating the dominant characteristic delay impact results with device fabrication and operation.

Coupling resistance and capacitance analysis systems and methods

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San Jose, CA, United States of America

Puneet Gupta