Intel Corporation

Puneesh Puri

James Jeong

Jiho Kang

Kevin J Lee

Hsiao-Kang Chang

John Muirhead

Adwait Telang

Nitin M Patel

Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together.

Through-body via liner deposition

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a 'plate through resist' type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

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Bengaluru, India

Puneesh Puri