Intel Corporation

Pulkit Jain

Fatih Hamzaoglu

Liqiong Wei

Ravi Pillarisetty

Niloy Mukherjee

Stefan Rusu

Uday Shah

Muhammad M Khellah

James S Clarke

Prashant Majhi

James W Tschanz

Elijah V Karpov

Bernhard Sell

Yih Wang

Wilfred Gomes

Charles Augustine

Mark Armstrong

Travis W LaJoie

Pei-Hua Wang

Chieh-Jen Ku

Carlos Alfonso Tokunaga

Juan G Alzate-Vinasco

Umut Arslan

Aravind S Killampalli

Nathaniel August

Jay P Gupta

James D Waldemer

Rangharajan Venkatesan

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

Decoupling capacitors and methods of fabrication

An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

Resistive random access memory with deuterium

Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device.

Apparatuses and methods to control operations performed on resistive memory cells

An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

Resistive memory write circuitry with bit line drive strength based on storage cell line resistance

Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Memory cell with retention using resistive memory

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Hillsboro, OR, United States of America

Pulkit Jain