Qualcomm Incorporated

Prudhvi Nadh Nooney

Mark Michael Schaffer

Jaya Prakash Subramaniam Ganasan

Richard Gerard Hofmann

Ryan Donovan Wells

Barry Joe Wolford

Perry Willmann Remaklus, Jr

Darren P Umstead

Vijay Nagaraj

Joseph L Van Swearingen

Systems and methods for relate to bus ring performance monitoring and control. A bus ring includes an agent and a switch unit to connect the agent to the bus ring. The switch unit includes a transmit queue to store data from the bus ring to be transmitted to the agent and a receive queue to store data from the agent to be transmitted to the bus ring. A first counter is implemented to track a number of pending transactions in the transmit queue and a second counter is implemented to track a number of times the receive queue is full and unable to accept additional data. Frequency of the bus ring is increased or decreased based on comparison of values of the first counter and the second counter with corresponding predefined high and low threshold values.

Monitoring and controlling bus ring performance

Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.

Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods

A transaction request passes from an initiator through interconnect paths and a routing ID indicating the interconnect paths is prepended. A temporary ID is assigned to the routing ID, the transaction request with the temporary ID is sent to a target device, and a response having the temporary ID is received. The routing ID is retrieved using the target ID, and the response with the retrieved routing ID is sent to the initiator.

Method and apparatus for scalable network transaction identifier for interconnects

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Raleigh, NC, United States of America

Prudhvi Nadh Nooney