Synopsys, Inc.

Pronay Kumar Biswas

Paras Mal Jain

Abhinav Singla

A method of performing static verification of a circuit design that includes a number of circuit blocks, includes, in part, receiving a first model of a first block generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a multitude of verification tests performed by the first version of the tool as well as associated first setup information. In response to the determination that, for each of the of tests performed, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design are regenerated.

Growing community of inventors

Sunnyvale, CA, United States of America

Pronay Kumar Biswas