Qualcomm Incorporated

Priyatharshan Pathmanathan

Siamak Fazelpour

John A Loffink

Devarshi Patel

Kyle Roberts

Dennis Allen Northgrave

A system includes: a printed circuit board having a plurality of conductive traces; a processing device coupled to the printed circuit board and in electrical communication with the plurality of conductive traces; a first memory module and a second memory module in electrical communication with the plurality of conductive traces and sharing channels of the conductive traces, wherein the first memory module is physically more proximate to the processing device than is the second memory module; and an electronic band gap (EBG) structure physically disposed in an area between the first memory module and the second memory module.

Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling

An electrical device including a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer.

Circuits and methods providing mutual capacitance in vertical electrical connections

Methods and apparatuses for reducing excess on die capacitance. The method couples a first die pad to a first via. The method couples a second die pad to a second via. The method couples a first inductor to the first die pad and the second via. The method couples a second inductor to the second die pad and the first via.

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Wake Forest, NC, United States of America

Priyatharshan Pathmanathan