Cadence Design Systems, Inc.

International Business Machines Corporation

Priyanka Dasgupta

Vivek Chickermane

Jagjot Kaur

Anshul Sheopuri

Priyanka Agrawal

Nandakishore Kambhatla

Saikat Mukhopadhyay

Aditya Telang

Nickle Lamoreaux

Binny Rieder

Joanna Daly

Gopi Kudva

Pooja Arya

Pratyush Aditya Kothamasu

Various embodiments are provided for implementing intelligent decision support system in a computing environment by a processor. Data of historical decisions may be collected and examples of decisions by domain experts may be generated. One or more machine learning models may be generated using different splits of the historical data and the annotated data. The one or more machine learning models may be combined and used to generate ensemble machine learning models that generate recommendations for the decisions. Users interact with a user interface displaying the data, recommendations, reasons for recommendations and a conversational dialog system for querying about the data, recommendations and guidance for decision making.

Intelligent decision support system

Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.

Devices and methods for test point insertion coverage

Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.

Power and scan resource reduction in integrated circuit designs having shift registers

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Bengaluru, India

Priyanka Dasgupta