Applied Materials, Inc.

Other

Priyadarshi Panda

Sanjay S Natarajan

Gill Yong Lee

Sung-Kwan Kang

Lei Lian

Leonard Michael Tedeschi

Jonathan C Shaw

In Seok Hwang

Seshadri Ganguli

Todd J Egan

Sang Ho Yu

Jianxin Lei

Pengyu Han

Lequn Liu

Nobuyuki Sasaki

Prashant Aji

Jorge Pablo Fernandez

Eli Mor

Alex J Tom

Rajib Lochan Swain

Ning Li

Srinivas Gandikota

Mihaela A Balseanu

Gene S Lee

Nancy Fung

Wenting Hou

Chaitanya Sharma

Yongchang Dong

Somaye Rasouli

A cool cluster comprises one or more transfer chambers; a plurality of process chambers connected to the one or more transfer chambers; and a computing device of the tool cluster. The computing device is to receive first measurements generated by sensors of a first process chamber during or after a process is performed within the first process chamber; determine that the first process chamber is due for maintenance based on processing the first measurements using a first trained machine learning model; after maintenance has been performed on the first process chamber, receive second measurements generated by the sensors during or after a seasoning process is performed within the first process chamber; and determine that the first process chamber is ready to be brought back into service based on processing the second measurements using a second trained machine learning model.

Autonomous substrate processing system

A substrate processing system comprises an etch chamber configured to perform an etch process on a substrate, the etch chamber comprising an optical sensor to generate one or more optical measurements of a film on the substrate during and/or after the etch process. The system further comprises a computing device operatively connected to the etch chamber, wherein the computing device is to: receive the one or more optical measurements of the film; determine, for each optical measurement of the one or more optical measurements, a film thickness of the film; determine an etch rate of the film based on the one or more optical measurements using the determined film thickness of each optical measurement of the one or more optical measurements; and determine a process parameter value of at least one process parameter for a previously performed process that was performed on the substrate based on the etch rate.

Etch feedback for control of upstream process

Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.

Method of processing dram

A substrate processing system comprises one or more transfer chambers; a plurality of process chambers connected to the one or more transfer chambers; and a computing device connected to each of the plurality of process chambers. The computing device is to receive first measurements generated by sensors of a first process chamber during or after a process is performed within the first process chamber; determine that the first process chamber is due for maintenance based on processing the first measurements using a first trained machine learning model; after maintenance has been performed on the first process chamber, receive second measurements generated by the sensors during or after a seasoning process is performed within the first process chamber; and determine that the first process chamber is ready to be brought back into service based on processing the second measurements using a second trained machine learning model.

A method of patterning a substrate is provided. The method includes modifying a surface of a metal-containing layer formed over a substrate positioned in a processing region of a processing chamber by exposing the surface of the metal-containing layer to plasma effluents of a chlorine-containing gas precursor and an oxygen-containing gas precursor to form a modified surface of the metal-containing layer. The method further includes directing plasma effluents of an inert gas precursor towards the modified surface of the metal-containing layer. The plasma effluents of the inert gas precursor are directed by applying a bias voltage to a substrate support holding the substrate. The method further includes anisotropically etching the modified surface of the metal-containing layer with the plasma effluents of the inert gas precursor to form a first recess having a first sidewall in the metal-containing layer.

Selective anisotropic metal etch

A process of smoothing a top surface of a bit line metal of a memory structure to decrease resistance of a bit line stack. The process includes depositing titanium layer of approximately 30 angstroms to 50 angstroms on polysilicon layer on a substrate, depositing first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on titanium layer, annealing substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on first titanium nitride layer after annealing, depositing a bit line metal layer of ruthenium on second titanium nitride layer, annealing bit line metal layer at temperature of approximately 550 degrees Celsius to approximately 650 degrees Celsius, and soaking bit line metal layer in hydrogen-based ambient for approximately 3 minutes to approximately 6 minutes during annealing.

Methods and apparatus for smoothing dynamic random access memory bit line metal

Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

Method of testing a gap fill for DRAM

Method of processing DRAM

Gap fill methods of forming buried word lines in DRAM without forming bottom voids

A process of smoothing a top surface of a bit line metal of a memory structure decreases resistance of a bit line stack. The process includes depositing a titanium layer of approximately 30 angstroms to 50 angstroms on a polysilicon layer on a substrate, depositing a first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on the titanium layer, annealing the substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing a second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on the first titanium nitride layer after annealing, and depositing a bit line metal layer of ruthenium on the second titanium nitride layer.

A system of generating water from the air in the most energy efficient manner is provided. The water generating apparatus uses a combination of rotating pre-loader wheels of separation materials, mechanical condensation system such as Vapor Compression Cycle (VCC), filtration and mineral addition units to create an energy efficient system for generating water from ambient air. An IoT water generating apparatus optimized through systems integration including smart controls and programming board for optimizing water production using weather and utility data for energy efficient water production from ambient air.

Economically viable atmospheric water generator

Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

Cap layer for bit line resistance reduction

Methods and apparatuses for substrate fabrication are provided herein. The apparatus, for example, can include a cluster tool including a vacuum transfer module (VTM) configured to receive, under vacuum conditions, a silicon substrate with a polysilicon plug (poly plug) and transfer, without vacuum break, the substrate to and from a plurality of processing chambers each independently connected to the VTM for performing a corresponding one of a plurality of DRAM bit line processes on the substrate, the plurality of processing chambers comprising a pre-cleaning chamber configured to remove native oxide from a surface of the substrate, a barrier metal deposition chamber configured to deposit the barrier metal on the surface of the poly plug on the silicon substrate, a barrier layer deposition chamber configured to deposit at least one material on the surface of the barrier metal, a bit line metal deposition chamber configured to deposit at least one material on the surface of the barrier layer, and a hard mask deposition chamber configured to deposit at least one material on the surface of the bit line metal.

Growing community of inventors

Newark, CA, United States of America

Priyadarshi Panda