Altera Corporation

Priya Selvaraj

Peter John McElheny

Francois Gregoire

Irfan Rahim

Bradley Jensen

Hugh Sung-Ki O

Girish Venkitachalam

Yow-Juang (Bill) Liu

Bill Yowjuang Liu

Susan Falk

Disclosed is a method for checking the operation of an IC mask generation algorithm in which at least a first identifier of the mask generation algorithm is associated with at least a first symbol that is not associated with generating a functional IC feature. The first symbol has a predetermined size and a predetermined shape. A predetermined location on a mask is also associated with the first symbol. A mask diagram on the mask is generated at least partially at the first predetermined location. The size and shape of the mask diagram is then compared with at least a portion of the first predetermined size and the first predetermined shape of the first symbol.

Method and system for checking operation of a mask generation algorithm

A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.

Polysilicon gate doping level variation for reduced leakage current

A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.

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Sunnyvale, CA, United States of America

Priya Selvaraj