Marvell International Limited

Intel Corporation

Priya N Vaidya

Premanand Sakarda

Bryan C Morgan

Marlon Moncrieffe

Moinul H Khan

Yu Bai

Yi Ge

Michael D Rosenzweig

Minda Zhang

Jia Bao

Scott B Peirce

Swee-chin Pang

Manoj I Thadani

Palanisamy Mohanraj

Kalpana Mittal

Zhou Gao

Canhui Yuan

In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

System for managing power provided to a processor or memory based on a measured memory consumption characteristic

Dynamic processor core switching is described. In embodiments, a multi-core processor system can include a first processor core that executes computer instructions at a first processing rate, and can include at least a second processor core that executes the computer instructions at a second processing rate, where the second processing rate is different than the first processing rate. A core profiler can generate system profile data that is evaluated to determine when a core-switch manager initiates switching execution of the computer instructions from the first processor core to the second processor core while the computer instructions are being executed.

Dynamic processor core switching

A mobile electronic communication device power management method and apparatus are disclosed for use in multiple processor hardware schemes having asymmetrical power demands between processors. Upon reaching an long duration idle state, a high-level processor with high power consumption requirements handling low-level system tasks updates a data set shared between processor subsystems containing information necessary to perform such low-level tasks. A proxy software module is initiated on a base-band processor with lower power consumption requirements. The proxy module accesses the shared data set and begins to control low-level system tasks, allowing the high-level processor to enter a dormant low power state. Upon the occurrence of a wake-up event, the high-level processor enters an active state. The shared data set is updated by the proxy software module and the proxy module is terminated. The high-level processor accesses the shared data set and resumes control of low-level system tasks.

Methods and apparatus for power mode control for PDA with separate communications and applications processors

Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.

Method and system for selecting an operating frequency for a chip to provide a desired overall power dissipation value for the chip

Power management in electronic systems

A display system is disclosed. The display system has a processor, a memory, a display device, a display controller configured to control the display device, and a bus connecting the processor, the memory, and the display controller. The display system also has a performance monitoring module configured to monitor events that occur on the bus during operation of the display system, and a performance profiling module configured to calculate, based on the monitored events, an available throughput of the processor on the bus. The display system also has a policy manager module configured to determine a refresh rate for the display controller such that a throughput on the bus required by the display controller is less than the calculated available throughput.

Systems and methods for reducing display under-run and conserving power

A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.

System and method for adaptive power management based on processor utilization and cache misses

A disclosed method involves initializing a performance profiler of a processing system. The performance profiler may include performance profile parameters for a power management policy for the processing system. The method also involves retrieving performance metrics for the processing system from a performance monitoring unit (PMU) of the processing system, in response to a determination that performance details should be collected. A current performance state of the processing system may be determined, based at least in part on the performance profile parameters and the performance metrics from the PMU. The current performance state may then be communicated to a policy manager of the processing system. Other embodiments are disclosed and claimed.

System and method for adaptive power management

A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.

Least mean square dynamic cache-locking

A method and apparatus to perform memory management are described.

Growing community of inventors

Shrewsbury, MA, United States of America

Priya N Vaidya