Intel Corporation

Priya Autee

Edwin Verplanke

Andrew J Herdrich

Patrick Lu

Vivekananthan Sanjeepan

Mrittika Ganguli

Abhishek Khade

Abhirupa Layek

Lin Yang

Rajesh M Sankaran

Reshma Lal

Ren Wang

Jr-Shian Tsai

Sameh Gobriel

Anjali Singhai Jain

Narayan Ranganathan

Rahul R Shah

Iosif Gasparakis

Jeffrey D Chamberlain

Malini Krishnan Bhandaru

Nilesh K Jain

Brinda Ganesh

Yipeng Wang

Somnath Paul

Chih-Jen Chang

Abhijit Davare

Sriram Kabisthalam Muthukumar

Sunku Ranganath

Anton Alexandrovich Sorokin

Desmond A Kirkpatrick

Suvadeep Banerjee

Nupur Jain

Dakshina Ilangovan

Shaohe Feng

Rui Zang

Liyong Qiao

Omkar Maslekar

Shaman Narayana

Jaykant B Timbadiya

Nalini Murari

Lin A Yang

Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

Network layer 7 offload to infrastructure processing unit for service mesh

Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

Controller for locking of selected cache regions

Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

Hardware offload circuitry

Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

Cache line demote infrastructure for multi-processor pipelines

A holistic view of cache class of service (CLOS) to include an allocation of processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.

Techniques to support a holistic view of cache class of service for a processor cache

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Chandler, AZ, United States of America

Priya Autee