Sandisk Technologies Inc.

Primit Modi

Venkatesh Ramachandra

Tianyu Tang

Sung-En Wang

Srinivas Rajendra

Khin Htoo

Supraja Sundaresan

Disclosed is a device including a selected distributed driver, a first feedback control circuit, and a second feedback control circuit. The first feedback control circuit is coupled to the selected distributed driver. The first feedback control circuit is configured to maintain an output of the selected distributed driver within a first predetermined range. The second feedback control circuit is selectively coupled to the selected distributed driver and is configured to maintain the output of the selected distributed driver to be within a second predetermined range. The second predetermined range is within the first predetermined range.

Bias control circuit with distributed architecture for memory cells

A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.

Duty cycle correction scheme for complementary signals

A driver circuit, such as could be used as an off-chip driver for an I/O pin on a memory circuit, is presented. The driver has a PMOS connected between a supply level and the driver's output node. In an active mode, the bulk terminal of the PMOS is connected to the supply level; and in a standby mode, the PMOS's bulk terminal is set to a higher level. This reduces the leakage current through the PMOS in the standby mode, allowing for smaller device with a lower capacitance to be used.

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