International Business Machines Corporation

Price Ward Oman

Frank J Pita

Brian Mitchell Bass

Richard Allen Kelley

James Allison Hubbard

Danny Marvin Neal

Patrick Allen Buckland

Mark Anthony Rinaldi

Gregory Salyer

Joseph Curtis Diepenbrock

Donald W Price

Hartmut Ulland

Richard Charles Paddock

Andrew J Rindos, Iii

Arthur Wilbert Holmes, Jr

Guenter Hahn

Carl Raymond Waters

Vito W Russo

Klaus Muenzner

Melvin Kent Benedict

Method and system for controlling the state of a system bus during live insertion and removal of a pluggable feature card (FC) by driving control signals, which are transferred over the system bus, to an active signal level, or by driving down level active control signals to a low signal level near ground level. By this mechanism, the system bus becomes immune to signal disturbances and thereby allows pluggable units to be live inserted and removed without causing adverse effects to the system such as a system reset or compromise of data integrity. During live insertion or removal, a Live Insertion Bus Controller (LIBC) acquires access to the system bus through its interface with a System Bus Controller (SBC), after it has been signalled by a live insertion mechanism associated with the FC that the FC is in the process of being live inserted or removed. After system bus access has been acquired by the LIBC and the LIBC has taken over the control of the system bus, it drives a subset of the system bus set of control signals to a state that is immune from insertion/removal signal disturbance. In parallel, the LIBC effects suspension of running timeout and watchdog operations currently being performed by the SBC. When the LIBC is informed that the insertion process has been completed, the SBC again acquires control of the system bus. The same procedural steps are performed in case of removal of an FC.

Method and system for enabling nondisruptive live insertion and removal

A computer system is provided which allows a user to remove or install feature cards without removing the cover to entire computer. A computer cover is provided with rectangular openings which correspond in alignment and size to an electrical connector on the system board. The feature card can then be mechanically attached to the computer cover, or a frame member, with a pivot and guide member. A handle is provided which will allow the user to apply pressure to the card, via the guide member in order to insert or remove the feature card from the connector on the system board. The guide member is constructed such that a vertical force is applied between the card and connector to ensure proper alignment when inserting and removing the adapter card.

Autodocking hardware for installing and/or removing adapter cards

The invention is related to hot plugging of an electrical circuit (1) into a separate non-quiesced signal net (6) in an active system (7), such as a digital or analog bus. The inventive solution proposes the addition of a preconditioning network (4) to precondition the electrical circuit (1) to be hot plugged by partially precharging the parasitic input capacitances (C.sub.c, C.sub.e, C.sub.m) of the electrical circuit (1) before hot plugging. The precharging of the parasitic input capacitances serves to minimize transient effects on the active system (7).

Precharge for non-disruptive bus live insertion

A central arbiter uses priority generators to determine which resource on a shared bus has priority in accessing the bus. Each resource has a corresponding priority generator. Each priority generator has a counter having inputs and outputs. A starting value is provided at the inputs and the priority value is obtained from the outputs. Each priority generator has a comparator that compares the outputs of a counter with a modulo number of the counters, N. The priority generators provide a combination of fixed priority and round robin arbitration schemes. By selecting the value of N relative to the number of resources, the rate of round robin access relative to fixed priority access can be set.

Priority generator for providing controllable guaranteed fairness in

A uniprocessor if formed on plural independently controlled chips each including a primary instruction driven controller and a secondary error driven self-sequencing controller. Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line. Hardware monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch driving a common external ERROR line, an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.

Detection and correction of multi-chip synchronization errors

A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.

Distributed execution processor

Growing community of inventors

Raleigh, NC, United States of America

Price Ward Oman