Advanced Micro Devices Corporation

Preyesh Dalmia

Michael Warren Boyer

Rajesh Shashi Kumar

Matthew D Sinclair

A chiplet-based architecture provides for a reduction in cache synchronization operations by tracking a relationship between chiplet execution kernels and array operands to elide synchronization when particular arrays are not in use in the caches of other chiplets or when the current target chiplet already has the array operand. Further efficiency is promoted in some embodiments by assigning chiplets for reuse based on previously received arrays.

Cache synchronization for chiplet accelerators

Systems and methods of cache flushing include receiving, from a software application, a first cache flush request to perform a range-based cache flush of a contiguous virtual address range within a virtual memory that maps to a physical memory. A single cache walk is triggered via a second cache flush request to a cache. The single cache walk performs the range-based cache flush for the contiguous physical address range from a beginning address of the contiguous physical address range to an ending address of the contiguous physical address range in response to the first cache flush request.

Growing community of inventors

Madison, WI, United States of America

Preyesh Dalmia