Texas Instruments Corporation

Premkumar Seetharaman

Vinod J Menezes

Per Torstein Roine

Mahesh Madhukar Mehendale

Vamsi Gullapalli

Parvinder Kumar Rana

Vipul Kumar Singhal

Srinivasa Raghavan Sridhara

Atul Ramakant Lele

Raviprakash Suryanarayana Rao

Keshav Bhaktavatson Chintamani

Ajith Subramonia

Malav Shrikant Shah

Bharath Kumar Poluri

Sanjeev Kumar Suman

In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the SRAM circuit indicating that a series of SRAM cells along a selected row of SRAM cells will be accessed; a precharge first mode signal to the SRAM circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the SRAM circuit indicating that a last access along the selected row will occur. The SRAM circuit includes an array of SRAM cells arranged in rows and columns to store data. Each SRAM cell is coupled to: a corresponding word line along a row of SRAM cells; and a corresponding pair of complementary bit lines.

Circuits and methods for performance optimization of SRAM memory

A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to receive a precharge signal and a word line signal and identify consecutive reads from storage cells accessed via a same one of the word lines. The read controller is further configured to, based on the precharge signal and the word line pulse signal indicating that the SRAM is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines after each read of the consecutive reads.

Burst mode read controllable SRAM

A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Automatic latch-up prevention in SRAM

In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

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Bengaluru, India

Premkumar Seetharaman