Altera Corporation

Preminder Singh

Peter John McElheny

Shankar Sinha

Shih-Lin S Lee

Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Multiport memory element circuitry

Adjustable positive voltage sag circuitry and adjustable ground bounce circuitry are provided for testing portions of integrated circuits. Adjustable positive voltage sag circuitry and adjustable ground bounce circuitry may provide positive power supply voltages with periodic sags and ground power supply voltages with periodic bounces to test a circuit under test. This may mimic a situation in which a circuit under test is surrounded by devices that switch simultaneously and consume power. Adjustable positive voltage sag circuitry and adjustable ground bounce circuitry allow for a circuit under test to be tested for robustness under such non-ideal power supply conditions.

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Fremont, CA, United States of America

Preminder Singh