Intel Corporation

Marvell International Limited

Marvellworld Trade Ltd.

Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Compaq Information Technologies Group, L.p.

Premanand Sakarda

Priya N Vaidya

Bryan C Morgan

Marlon Moncrieffe

Yu Bai

Scott B Peirce

Jia Bao

Yi Ge

Sehat Sutardja

Guy M Therien

Lan Wang

Mark Norman Fullerton

James G Hermerding, Ii

Russell Jerome Fenger

Mingqiu Sun

Kelan Craig Silvester

Hong-Yi Chen

Michael D Rosenzweig

Chia-Hung Sophia Kuo

Minda Zhang

Ke Ding

Rajshree Chabukswar

Robert C Frame

Deepak Samuel Kirubakaran

Jay S Heeb

Hai Wu

Monica Gupta

Jianwei Dai

Jian Sun

Ofer Zaarur

Richard Quinzio

Yuyang Du

Yong Tong Chua

Renji Thomas

Ramakrishnan Sivakumar

Swee-chin Pang

Manoj I Thadani

Richard Hennessy

Zhou Gao

Canhui Yuan

Sebastien Haezebrouck

Todd Brandt

Leo Aqrabawi

Nicole Chalhoub

Bijan Arbab

Sreedhar Varma

Mark Sawyer

Chad Gutierrez

Palanisamy Mohanraj

Jay Heeb

A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

Hardware and software coordinated cost-aware low power state selection

A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.

Intelligent prediction of processor idle time apparatus and method

Various systems and methods for virtual CPU consolidation to avoid physical CPU contention between virtual machines are described herein. A processor system that includes multiple physical processors (PCPUs) includes a first virtual machine (VM) that includes multiple first virtual processors (VCPUs); a second VM that includes multiple second VCPUs; and a virtual machine monitor (VMM) to map individual ones of the first VCPUs to run on at least one of, individual PCPUs of a first subset of the PCPUs and individual PCPUs of a set of PCPUs that includes the first subset of the PCPUs and a second subset of the PCPUs, based at least in part upon compute capacity of the first subset of the PCPUs to run the first VCPUs, and to map individual ones of the second VCPUs to run on individual ones of the second subset of the PCPUs.

Virtual CPU consolidation to avoid physical CPU contention between virtual machines

In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

System for managing power provided to a processor or memory based on a measured memory consumption characteristic

In one embodiment, a policy manager may receive operating system scheduling information, performance prediction information for at least one future quantum, and current processor utilization information, and determine a performance prediction for a future quantum and whether to cause a switch between asymmetric cores of a multicore processor based at least in part on this received information. Other embodiments are described and claimed.

Dynamically switching a workload between heterogeneous cores of a processor

Dynamic processor core switching is described. In embodiments, a multi-core processor system can include a first processor core that executes computer instructions at a first processing rate, and can include at least a second processor core that executes the computer instructions at a second processing rate, where the second processing rate is different than the first processing rate. A core profiler can generate system profile data that is evaluated to determine when a core-switch manager initiates switching execution of the computer instructions from the first processor core to the second processor core while the computer instructions are being executed.

Dynamic processor core switching

Systems, methods, and other embodiments associated with a processor configured with a zero power hibernation/sleep mode during which the processor consumes no power are described. According to one embodiment, a processor includes a power management logic. The power management logic is configured to receive a control signal requesting the processor to transition into a power saving mode that reduces power to the processor while retaining a current state of the processor. The power management logic is configured to store, in response to the control signal, a current state of components of the processor in a non-volatile memory. The power management logic is configured to adjust power to the processor to a zero power mode to place the processor into the power saving mode, wherein during the zero power mode the processor is receiving no power.

Zero power hibernation mode with instant on

A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

Dynamic core switching

The present disclosure describes techniques and apparatuses for switching between processor cache and random-access memory. In some aspects, the techniques and apparatuses are able to reduce die size of application-specific components by forgoing dedicated random-access memory (RAM). Instead of using dedicated RAM, a memory having a cache configuration is reconfigured to a RAM configuration during operations of the application-specific component and then, when the operations are complete, the memory is configured back to the cache configuration. Because many application-specific components already include memory having the cache configuration, reconfiguring this memory rather than including a dedicated RAM reduces die size for the application component.

Switching between processor cache and random-access memory

The present disclosure describes techniques for switching tasks between heterogeneous cores. In some aspects it is determined that a task being executed by a first core of a processor can be executed by a second core of a processor, the second core having an instruction set that is different from that of the first core, and execution of the task is switched from the first core to the second core effective to decrease an amount of energy consumed by the processor.

Switching tasks between heterogeneous cores

Some of the embodiments of the present disclosure provide a method comprising generating a plurality of power profiles for a corresponding plurality of processing cores, wherein each power profile of the plurality of power profiles includes power consumptions of a corresponding processing core under various operating conditions; generating a plurality of candidate configurations, wherein each candidate configuration comprises corresponding candidate operating conditions for the plurality of processing cores; and based at least in part on the plurality of power profiles, selecting a first candidate configuration of the plurality of candidate configurations for managing the plurality of processing cores. Other embodiments are also described and claimed.

System and method for selecting a power management configuration in a multi-core environment to balance current load demand and required power consumption

System and method for selecting a power management configuration in a multi-core environment according to various operating conditions such as voltage, frequency, power mode, and utilization factor varied on a per-core basis

Apparatus having corresponding methods comprise a processing core performance monitoring module adapted to receive indications of performance levels of a plurality of processing cores, the plurality of processing cores comprising a central processing unit (CPU), a video accelerator, and a graphics accelerator; a video accelerator performance monitoring module adapted to receive an indication of a performance level of the video accelerator; a graphics accelerator performance monitoring module adapted to receive an indication of a performance level of the graphics accelerator; and a processor core management module adapted to dynamically allocate at least one of a pre-processing task and a post-processing task of a multimedia workload to any one of the video accelerator, the graphics accelerator, and the CPUprocessing cores based on the performance levels of the video accelerator, the graphics accelerator, and the CPU.

Dynamic processing core selection for pre- and post-processing of multimedia workloads

Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.

Method and system for selecting an operating frequency for a chip to provide a desired overall power dissipation value for the chip

Methods and systems for a multi-core processing system are described. In one embodiment, an apparatus comprises a first operating system (OS) core for managing kernel services. The first OS core includes a first physical memory, a first memory manager, and a first scheduler for scheduling a process to be executed, wherein the process is associated with a plurality of threads. At least two second OS cores comprise a second OS core and a third OS core. The apparatus includes a shared memory manager and a shared scheduler that are shared by the at least two second OS cores. The shared memory manager and the shared scheduler are configured to communicate with the first memory manager and the first scheduler, respectively, to initiate offloading of one or more of the threads from the first OS core to at least one of the at least two second OS cores for execution.

Power optimization for multi-core devices having a shared memory manager

Growing community of inventors

Acton, MA, United States of America

Premanand Sakarda