Cadence Design Systems, Inc.

Preeti Kapoor

Sanjib Ghosh

Sravasti Gupta Nair

Hongzhou Liu

Hui Xu

Chandra Prakash Manglani

Subhashis Mandal

Nikhil Garg

Kanaka Raju Gorle

Anup Kumar Lohiya

Disclosed is an improved approach to implement analog or mixed-signal designs. A method, system, and computer program product are provided to fully automate the analog placement step using a virtual grouping methodology which considers variable components and uses a genetic placement algorithm to find the best placement solution which fully respects the analog constraints defined by a user or auto identified by a tool.

Automatic placement of analog design components with virtual grouping

A method including creating a plurality of component groups in a circuit layout coupling multiple components in each component group of the plurality of component groups with a power rail, a ground rail, or a bulk, is provided. The method includes creating internal clusters based on a group cost and including the group cost in an overall cost function, forming a gap between two component groups of the plurality of component groups, and filling the gap with a first gap cell adjacent to a first power rail and to a first ground rail, and a second gap cell adjacent to the first gap cell. A system and a non-transitory, machine readable medium storing instructions to perform the above method are also provided.

Power domain placement of circuit components in advance node custom design

A circuit editor generates a graphic rendering of an electronic circuit design for partial display in a visual canvas on a display unit. The circuit editor detects aberrant arrangements of circuit elements which violate predetermined circuit layout criteria, such as minimum spacing between the edges or corners of circuit elements, and forms a correction scheme to rearrange the circuit elements such that consistency with the circuit layout criteria is restored. When the aberrant arrangements are not themselves displayed in the visual canvas, the circuit editor generates visual indications of the layout violation and of the correction scheme, the latter being used to guide user correction of the violation.

Electronic circuit design editor with off-screen violation display and correction

An approach is described for implementing a GUI that provides a user interface for reviewing and correcting design rule violations within a CAD program. According to some embodiments, a user may enter a serial review process which may utilize contextual information to determine where to start that review process. Further, the serial review process may enable the user to review rule violations in an individual manner for a respective object. Furthermore, a dynamic directional violation identifier may be used to identify additional errors in the direction of movement, such as by processing a set of rules and parameters with respect to objects in the direction of movement. The serial review process and the dynamic directional violation identification may be combined in a single process such that as violations are reviewed, and corrections are attempted, they may be verified to determine if they generate additional violations.

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Noida, India

Preeti Kapoor