International Business Machines Corporation

Preetham M Lobo

Tobias Webel

Alper Buyuktosunoglu

Ramon Bertran Monfort

Pradeep Bhadravati Parashurama

Thomas Strach

Pradip Bose

Franco Motika

Cedric Lichtenau

Giora Biran

Phillip John Restle

Gerard M Salem

Christos Vezyrtzis

Richard Frank Rizzolo

Pierce I-Jen Chuang

Mitesh A Agrawal

John D Parker

Charles Robert Lefurgy

Malcolm Scott Allen-Ware

Tilman Gloekler

Bishop Chapman Brock

Srinivas Bangalore Purushotham

Andreas Koenig

Bulent Abali

Matthias Klein

Martin Recktenwald

James Douglas Warnock

Brian William Curran

Damir Anthony Jamsek

Ashutosh Misra

Rahul Rao

Razvan Peter Figuli

Vinod Bussa

Puja Sethia

Siva Sundar A

Ramon Betran Monfort

Archit Kapoor

Gaurav Sulagodu Venkatagiri

Embodiments relate to a system, program product, and method for mitigating voltage overshoot in one or more cores in a multicore processing device including a plurality of cores. The method includes determining, in real-time, an indication of power consumption within each core of the one or more cores. The method also includes determining, through the indication of power consumption, a voltage overshoot condition in the one or more cores. The method further includes increasing, for the one or more cores, a power demand thereof. The method also includes increasing, subject to the increasing the power demand, power delivery to the one or more cores, thereby at least arresting the rate of increase of the voltage overshoot.

Voltage overshoot management

A system for variable replacement in a template artificial intelligence (AI) accelerator code. The system includes: at least one memory; at least one processor communicatively coupled to the at least one memory, and configured for computing at least one table of variables from a template AI accelerator code; and an AI accelerator including a plurality of engines, and communicatively coupled to the at least one processor and the at least one memory. The AI accelerator is configured to create a variable replaced AI accelerator code for the plurality of engines of the AI accelerator from the template AI accelerator code by replacing variables in the template AI accelerator code with actual values from the at least one table of variables.

Variable replacement by an artificial intelligence accelerator

Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Proactive voltage droop reduction and/or mitigation in a processor core

Processing data in memory using a field programmable gate array by reading a first portion of a data set to a burst block having a first data format, transforming a sub-portion of the first portion, to an element block having a second data format, processing the sub-portion yielding a first results set, transforming the first results set to the first data format of the burst block, and writing the first results set to the burst block.

Processing data in memory using an FPGA

Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.

Fine resolution on-chip voltage simulation to prevent under voltage conditions

Embodiments relate to a system, program product, and method for proactively initiating throttle action on one or more cores in a multicore processing device to mitigate voltage droop therein. The method includes determining, in real-time, an indication of stall events within the core and determining one or more resolutions of the stall events. The method also includes determining, in real-time, a timing margin value for the core and predicting inducement of a voltage droop on the core. The method further includes integrating the resolutions of the stall events and the timing margin value for the core, determining, subject to the predicting, a throttle action for the core, and executing the throttle action on the core.

Voltage droop management through microarchitectural stall events

Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.

Record-based matching in data compression

Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.

Dynamically optimizing margins of a processor

Embodiments of the present disclosure relate to detecting undervoltage conditions at a subcircuit. A power supply current of a first subcircuit is determined over a first number of previous clock cycles. A cross current flowing between the first subcircuit and a second subcircuit is determined over the first number of previous clock cycles. An estimated momentary supply voltage present at the first subcircuit is then determined based on the power supply current of the first subcircuit over the first number of previous clock cycles and the cross current flowing between the first subcircuit and the second subcircuit over the first number of previous clock cycles.

Predictive on-chip voltage simulation to detect near-future under voltage conditions

Embodiments are disclosed for managing voltage droop. The techniques include performing a first determination that a timing margin is less than a first threshold. The techniques also include performing a second determination that an increase in processor activity exceeds a second threshold. Additionally, the techniques include determining that a voltage droop is indicated based on the first determination and the second determination. Further, the techniques include signaling a plurality of throttling circuits for a corresponding plurality of cores of a computer processor to actuate.

Mitigating voltage droop

An aspect includes a plurality of throttle controllers having a modular hierarchy comprising a plurality of levels within each of a plurality of processor cores that control a plurality of throttling actions. The throttling actions include dynamic adjustment of execution suspension within the processor cores. A plurality of input throttle events at each of the processor cores is resolved based on the modular hierarchy. A chip controller coupled to the processor cores can synchronize the throttling actions between the processor cores.

Multi-layered processor throttle controller

Examples of techniques for speculation throttling for reliability management are described herein. An aspect includes determining that a power state of a processor is above a speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the speculation throttling threshold, throttling speculation in the processor. Another aspect includes determining that the power state of the processor is above a power proxy threshold, wherein the power proxy threshold is higher than the speculation throttling threshold. Another aspect includes, based on determining that the power state of the processor is above the power proxy threshold, enabling a performance throttle unit of the processor.

Speculation throttling for reliability management

A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.

Distributed on chip network to mitigate voltage droops

Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.

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Bengaluru, India

Preetham M Lobo