Texas Instruments Corporation

Preetam Tadeparthy

Muthusubramanian Venkateswaran

Dattatreya Baragur Suryanarayana

Vikram Gakhar

Vikas Lakhanpal

Kuang-Yao Cheng

Kushal D Murthy

Wenkai Wu

Shobhit Singhal

Vishnuvardhan Reddy J

Sudeep Banerji

Mayank Jain

Brian Ashley Carpenter

Bhaskar Ramachandran

Rengang Chen

Manish Parmar

Evan Reutzel

Naga Venkata Prasadu Mangina

Bo Wang

Nancy Zhang

Nitin Kumar Agarwal

Rohit Narula

Karthik Anyam

Anindita Borah

Rama Venkatraman

Shuhua Zhang

Vishal Shaw

In an example, a circuit includes an emulated current generator configured to provide an emulated current signal responsive to a charge current and a discharge current. The emulated current signal can be representative of an emulated current through an output inductor. A comparator is configured to provide a comparator signal responsive to the emulated current signal and sensed current signal representative of a measure of current through the output inductor. An inductor code counter is configured to adjust an inductor code count value responsive to the comparator signal. A slope of the emulated current signal can be adjusted responsive to the inductor code count value.

Inductance detection for power converters

A DC-DC converter includes a current sense circuit. The current sense circuit includes a sense current output, an inductor current measurement circuit, an inductor current emulation circuit, a first switch, and a second switch. The inductor current measurement circuit has an output. The inductor current emulation circuit has an output. The first switch is coupled between the output of the inductor current measurement circuit and the sense current output. The second switch is coupled between the output of the inductor current emulation circuit and the sense current output.

DC-DC converter with hybrid current sensing

One example includes a VID signal decoder circuit. The circuit includes a coarse resolution decoder that receives a VID signal. The VID signal can be encoded with a digital value of an output voltage. The coarse resolution decoder can decode the VID signal to generate a first digital signal. The circuit also includes a fine resolution decoder that receives the VID signal and to decode the VID signal to generate a second digital signal. The circuit further includes a multiplexer to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal. The first and second states of the selection signal can be based on a relative amplitude of the first and second digital signals.

Voltage identification signal decoder

Aspects of the disclosure provide for a circuit, in some examples, including a storage element, a co-processor, and a telemetry sequencer coupled to the storage element and the co-processor. The telemetry sequencer is configured to implement a digital state machine to receive configuration information indicating a type of telemetry data for generation, retrieve operations and operands, where the operations and the operands define a sequential series of actions for execution to generate the telemetry data, drive the co-processor with the operations and the operands by passing some of the operations and some of the operands to the co-processor for processing by the co-processor, receive, from the co-processor, and store an intermediate output of the series of actions as the telemetry data in a first format, and receive, from the co-processor, and store a final output of the series of actions as the telemetry data in a second format.

Configurable circuit telemetry system

A circuit for a multi-phase power regulator including a power stage with a first phase and a second phase, the circuit including phase management circuitry coupled to the first phase and the second phase to control the first phase and the second phase, a first comparator coupled to an output of the multi-phase power regulator to compare a value of the output of the multi-phase power regulator to a first threshold value to produce a first comparison result, and phase shedding circuitry coupled to the first comparator and the phase management circuitry to control the phase management circuitry to activate or deactivate the second phase based at least partially on the first comparison result.

Multi-phase power regulator

An over/under voltage protection circuit includes a voltage input terminal, a digital-to analog converter, a comparator, and a control circuit. The comparator includes a first input coupled to an output of the digital-to-analog converter, and a second input coupled to the voltage input terminal. The control circuit includes an output coupled to an input of the digital-to-analog converter, and an input coupled to an output of the comparator. The control circuit is configured to set the digital-to-analog converter to generate an overvoltage fault threshold responsive to the output of the comparator indicating that voltage of a signal at the voltage input terminal exceeds a threshold currently generated by the digital-to-analog converter.

Over/under voltage detection circuit

A voltage regulator system includes a switch system including a power switch to conduct an output current through an inductor based on an input voltage and a switching signal to generate an output voltage at a load. A feedback system generates a PWM signal based on the output voltage and based on a variable reference voltage. A gate driver system generates the switching signal based on the PWM signal. The gate driver system controls the switch system to increase the output voltage at output voltage slopes in each of startup stages during startup of the voltage regulator system. A sampling system samples the output current and the output voltage during the startup of the voltage regulator system to measure each slope of the output voltage slopes at each of the respective startup stages during the startup of the voltage regulator system.

Multi-slope startup voltage regulator system

A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Fully differential current sensing

A control circuit for a DC-DC converter and a DC-DC converter are disclosed. The control circuit includes an integrator coupled to receive a first reference voltage and a first voltage that includes an output voltage for the DC-DC converter and to provide an integrated error signal. A first comparator is coupled to receive the first reference voltage and the first voltage and to provide a dynamic-integration signal that adjusts the integration time constant of the integrator.

Power converter with reduced undershoot and overshoot during load transients

In a described example, a method includes using a power supply, supplying an output voltage that varies in response to a reference voltage; detecting a voltage ramp in an input reference voltage; generating an offset voltage waveform; adding the offset voltage waveform to the input reference voltage to generate a second reference voltage; and using the second reference voltage, operating the power supply to supply the output voltage.

Methods and apparatus for overshoot, undershoot and delay reduction of a voltage regulator output by dynamically offsetting a reference voltage

An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either directly or via the buffer to the first external pin of the IC in order to calibrate the buffer.

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Bengaluru, India

Preetam Tadeparthy