Ams Sensors Germany Gmbh

X-fab Semiconductor Foundries Gmbh

Predrag Micakovic

Soeren Lohbrandt

Dalibor Stojkovic

Holger Haberla

Andrey Hudyryev

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating a first light wave by an emitter of the sensor system and detecting a second light wave by a detector of the sensor system. The second light wave is detected in response to the first light wave being reflected from a target object. The sensor system includes a first converter that obtains a first temperature measurement from a temperature sensor of the sensor system at least when the first light wave is generated or when the second light wave is detected. A temperature controller computes temperature coefficients to regulate a temperature of the sensor system. Each of the temperature coefficients are computed based on a difference between the first temperature and a reference temperature. The temperature controller generates a control signal to regulate the temperature of the sensor system based on the computed temperature coefficients.

Compensation of temperature effects in a sensor system

A method of processing an analog signal includes receiving, into signal processing circuitry from compensation circuitry, an offset compensation signal, the offset compensation signal having (i) a polarity opposite a polarity of a gain error of the signal processing circuitry and (ii) a magnitude equal to a nominal compensation value plus a deviation. The method includes generating, by the signal processing circuitry, an output signal based on an analog signal received into the signal processing circuitry, including applying the offset compensation signal to an intermediate signal generated by the signal processing circuitry. The method includes scaling the output signal based on the deviation between the magnitude of the offset compensation signal and the nominal compensation value.

Gain correction in signal processing circuitry

A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

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Erfurt, Germany

Predrag Micakovic