Pmc-Sierra, Inc.

Pmc-Sierra US, Inc.

Microsemi Storage Solutions (u.s.), Inc.

Predrag Acimovic

Vadim Milirud

Charles Kevin Huscroft

Tomas A Dusatko

Richard Hernandez

Parmanand Mishra

This disclosure provides methods and apparatus for processing differential signals having non-inverted and inverted signals. An example apparatus has first and second circuit arms, each arm connected to receive one of the input signals. Each arm has a main signal path for carrying the respective input signal, and a secondary signal path for carrying a voltage divided and low-pass filtered version of the respective input signal. The outputs of the main and secondary signal paths are combined to produce equalized output signals.

Apparatus and methods for variable peaking and low pass filtering equalization

A programmable passive peaking equalizer that can compensate for a frequency dependent loss of a variety of data channels is disclosed herein. Monotonic increase in signal loss vs. frequency of board traces, cables and even fiber causes significant distortion of transmitted data referred to as inter-symbol interference (ISI). Some embodiments of programmable passive equalizers disclosed herein can minimize ISI for a wide range of data channels with very low power penalty. Various embodiments of the passive equalizer can program the amount of peaking that occurs at the Nyquist frequency of the data rate, and hence compensates for high frequency signal loss. This in turn equalizes the high frequency patterns in the transmitted data stream, effectively eliminating the worst case ISI.

Programmable passive peaking equalizer

This disclosure provides methods and apparatus for processing differential signals having non-inverted and inverted signals. An example apparatus has first and second circuit arms, each arm connected to receive one of the input signals. Each arm has a post-cursor branch comprising a delay, an inverter and a series terminating resistance connected between the first input and a first circuit arm common node, and a main cursor branch comprising a buffer and a series terminating resistance connected between the first input and the first circuit arm common node. A first transformer has a primary winding connected between the first circuit arm common node and a first output and a secondary winding connected between an output of the buffer of the main cursor branch of the second arm and ground, with a capacitor and a resistor connected in series between the secondary winding and ground. A second transformer has a primary winding connected between the second circuit arm common node and a second output and a secondary winding connected between an output of the buffer of the main cursor branch of the first arm and ground, with a capacitor and a resistor connected in series between the secondary winding of the second transformer and ground.

Transformer based circuit for reducing EMI radiation in high speed CMOS SERDES transmitters

Methods and apparatus improve the signal integrity of high-speed integrated circuits. Disclosed is a passive network for an input to a receiver. One embodiment of the passive network has two coupled inductors to improve both return loss and insertion loss characteristics. A shunt inductor is connected in series with the termination resistance, while a series inductor is placed in series between the pad and receiver circuitry. By exploiting deliberately-introduced mutual coupling between these two inductors, an area-efficient passive network is created that improves both the return loss and input bandwidth.

Method and apparatus for improving the signal integrity of high-speed serial data receivers using coupled inductors

Apparatus and methods modulate the slew rate of high-speed edges of a differential digital signal. High-speed digital signals carried over printed circuit boards, backplanes, cables, and the like can radiate electromagnetic waves. These electromagnetic waves can cause electromagnetic interference (EMI), and are tightly regulated by appropriate agencies, such as the FCC. Common mode radiation from differential signals can also cause EMI. By modulating the slew rates of the rising and falling edges of the differential signal, and by applying negative feedback, symbol-rate related spurs can be spread over a wider frequency range than conventional spread spectrum clocking (SSC) techniques, and thus should generally be capable of greater EMI reduction than conventional SSC techniques.

Reduction of electromagnetic interference for differential signals

The present invention provides a novel structure that can be used to filter certain selected frequencies of common mode signals. The structure comprises a stub connected in parallel to a transmission line with termination at the end. It is suitable for implementation on printed circuit boards or backplanes, but it can be also used within the chip, either on die or package substrate. The structure can be also used as an equalizer, and can be used in designing an analog equalizer for high-speed circuits.

Loaded parallel stub common mode filter for differential lines carrying high rate digital signals

The present invention provides a novel structure that can be used to make a common mode filter. Only the common mode will be attenuated and the differential mode will not be attenuated. This structure can be implemented in a number of ways, a specific embodiment using strip-line and slot-line junctions is very compact and well-suited to use with multilayer PCBs, and does not require any extra components. It can be designed to attenuate certain discrete frequencies, by designing the poles of the transfer function to be at these frequencies.

Lowpass-bandstop common mode filter for differential lines carrying high rate digital signals

A desynchronizer for desynchronizing one or multiple channels of SONET/SDH data signals, which includes a first in first out (FIFO) buffer having an input coupled to said data signals and an output for outputting asynchronous data obtained from one or more of said SONET/SDH data channels. An arithmetic unit coupled to the FIFO performs all operations required for single or multi-channel desynchronization. An endless phase modulator is coupled to the arithmetic unit and to the FIFO and is operative, in response to input from the arithmetic unit, to produce a single output desynchronized clock or multiple output desynchronized clocks.

Multi-channel SONET/SDH desynchronizer

A phase detector for controlling a phase locked loop having a voltage controlled oscillator. A counter is clocked by a clock signal produced by the voltage controlled oscillator. A latch coupled to the counter is clocked by a modulated clock signal to latch values output by the counter. The modulated clock signal is produced by a phase modulator which modulates a synchronization clock reference signal. An accumulator coupled to the latch and clocked by the modulated clock signal receives and averages the latch values to produce a phase error signal representative of phase difference between the voltage controlled oscillator clock signal and the synchronization clock reference signal. The phase error signal is coupled to the voltage controlled oscillator to reduce the phase difference. The phase modulator modulates a rising edge of the synchronization clock reference signal with a modulation signal having modulation frequencies outside the loop bandwidth of the phase locked loop. The modulation signal is a discrete step signal having a fine time resolution which causes the latch to latch different values output by the counter in different time intervals corresponding to the time of occurrence of the modulated clock signal's rising edge with respect to the respective time intervals.

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Burnaby, Canada

Predrag Acimovic