Texas Instruments Corporation

Pravin P Patel

Roger D Norwood

Jim Childers

Chitranjan N Reddy

Kevin Patrick Lavery

Jino Chun

Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.

Method and system to reduce electromagnetic radiation from semiconductor devices

A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive load. Circuits inhibit turning ON the P-channel FET until the voltage on the gate of the N-channel FET falls below its turn-on voltage threshold, and turning ON the N-channel FET until the voltage on the gate of the P-channel FET falls below its turn-on voltage threshold.

Method of controlling slope and dead time in an integrated output buffer with inductive load

A circuit for assisting the charging of a line conductor having a distributed resistance and capacitance, such as a word line in a semiconductor memory device, is disclosed. In the conventional memory device, a driver circuit is disposed at one end of a word line, with a circuit for holding unselected word lines at the discharged voltage being disposed at the end of the word line opposite from the drive circuit. The invention is directed towards a pull-up circuit being disposed at the end of the word line opposite the driver circuit, the pull-up circuit having a transistor which is precharged to a high voltage prior to the active cycle. The precharged transistor is discharged as the selected word line is charged by the driver circuit, causing a driving node in the circuit to be connected to a high supply voltage. The driving node is connected to the word line by a transistor which is responsive to a select signal generated by the address decoder; once selected, the word line at the end opposite the driver circuit is driven by the high supply voltage. This will enable the selected word line to be pulled up to the high supply voltage at both ends, thereby reducing the time required to charge the word line to the required voltage level. The pull-up circuit may also include a transistor for holding the word line low, if unselected; this transistor is made non-conductive as the precharged transistor is discharged. Further disclosed is a circuit which allows a plurality of word lines to share the precharging and driving transistors, but which dedicates for each word line the 'bleeder' transistor for holding unselected word lines low and the transistors for coupling the driving node to the word line. In addition, a circuit which provides a reduced voltage at the bleeder transistor, thereby speeding up the charging of the word line by the driver circuit, is disclosed.

Pull-up circuit for high impedance word lines

A semiconductor dynamic memory device is disclosed which contains circuitry for implementing both page mode and nibble modes using a conductor level selection. A clock voltage used in column decoding and output is either coupled to or decoupled from the column strobe or CAS input by conductor, so this clock voltage is rendered either dependent on, or independent of, the cycling of the column strobe.

Semiconductor dynamic memory device with metal-level selection of page

A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output from the array. Single-bit data-in and data-out terminals for the device are coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and the latched address includes the address of the starting bit within the 4-bit sequence for serial I/O. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence. To reduce power dissipation, the inverter stages of the ring counter are operated by pulsed clocks generated from the asynchronous memory control clocks received from the CPU.

High speed, low-power nibble mode circuitry for dynamic memory

A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output. Single-bit data-in and data-out terminals for the device may be coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and this includes the address of the starting bit within the 4-bit sequence. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence.

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Sugar Land, TX, United States of America

Pravin P Patel