International Business Machines Corporation

Seagate Technology Incorporated

Pure Storage, Inc.

Praveen Viraraghavan

Ilya Volvovski

Andrew D Baptist

Manish Motwani

Jason K Resch

Ethan S Wozniak

Greg R Dhuse

Ravi V Khadiwala

Jon David Trantham

Mohamad H El-Batal

John West Dykes

Darshana H Mehta

Ian James Gilbert

Matthew J Totin

Sangita Shreedharan Kalarickal

Wesley B Leggette

Jordan Harrison Williams

Scott Michael Horan

Ying Zhao Guo

Benjamin Lee Martin

Trevor J Vossberg

Steven Scott Williams

Robert William Dixon

Marc Timothy Jones

Jason Matthew Feist

Bart Richard Cilfone

Adam Michael Gray

Niall John McShane

Teague Scott Algie

Ram S Narayanan

Amit H Lamba

Hemant Vitthalrao Mane

Mark Alfred Lantz

Mark A Gaertner

John Michael Bent

Asimuddin Kazi

Ilias Iliadis

Kumar Abhijeet

Daniel J Scholl

Abhay Tejmal Kataria

Bruno Hennig Cabral

Patrick Aaron Tamborski

Joseph M Kaczmarek

Franco Vincent Borich

Tyler K Reid

Trent William Johnson

Michael J Niedbala

Gregory A Papadopoulos

David Brittain Bolen

Peter C Kim

Fnu Manupriya

Anuraag Shah

Sridhar Gopalam

Khushbu Patel

Russell C Fordyce

Tim Shaffer

Akiko Sato

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

Intelligent management of ferroelectric memory in a data storage device

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

Balancing power, endurance and latency in a ferroelectric memory

A distributed data storage system can be configured with a host connected to a device and a distribution module. The distribution module identifies a manufacturing origin of the device and diverts a system operation from an upstream component connected to the distribution module to the device in response to the identified manufacturing origin of the device. The manufacturer installed operating parameters of the device are then used to complete the system operation.

Data storage system with distributed operations for known hardware

A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

System on chip (SOC) with processor and integrated ferroelectric memory

A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

Read destructive memory wear leveling system

A distributed data storage system may connect a host to a device and a dedication module. The dedication module can identify a manufacturing origin of the device before dedicating a type of host-generated data access request to the device. The type of host-generated data access request is chosen by the dedication module in response to an operating capability correlated to the device by the dedication module based on the identified manufacturing origin. At least one host-generated request of the dedicated type is then completed with the device.

Distributed data storage system with dedicated processing lane

A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

Non-volatile memory cell with multiple ferroelectric memory elements (FMEs)

A distributed data storage system can be configured with a host connected to a first device and an initialization module that performs a default initialization procedure on the first device in response to detecting the first device has an unknown manufacturing origin. Conducting the default initialization procedure may allow the first device to service data access requests from the host. In response to the connection of a second device to the host and initialization module, a manufacturing origin of the second device is identified with the initialization module before the initialization module customizes the default initialization procedure to a custom procedure that is executed to allow the second device to satisfy a background operation prescribed by the initialization module.

Custom initialization in a distributed data storage system

A data storage system may connect a host to a device and a hardware module that are utilized to satisfy at least one host-generated data access request to the device. A portion of the device is set as dormant by the hardware module prior to identifying an origin of the device with the hardware module during the satisfaction of the at least one host-generated data access request. In response to the identified origin, the previously dormant portion of the device is activated and subsequently utilized to execute a task assigned by the hardware module.

Distributed data storage system with dormant hardware activation

A data storage device includes at least one data storage medium. The data storage device also includes a workload rating associated with data access operations carried out on the at least one data storage medium. The data storage device further includes a controller configured to enable performance of the data access operations, and change a rate of consumption of the workload rating by internal device management operations carried out in the data storage device in response to a change in a workload consumed by host commands serviced by the data storage device.

Workload amplification metering and management

Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

Stack register having different ferroelectric memory element constructions

A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.

Front end buffer having ferroelectric field effect transistor (FeFET) based memory

A method for execution by a storage unit in a dispersed storage network (DSN) includes selecting a storage zone of a memory device of the storage unit based on zone allocation parameters, and designating the selected storage zone as open for writes. A data slice is received via a network for storage. The data slice is written sequentially at a memory location of the one of storage zone based on determining that the storage zone is designated as open for writes. A pointer corresponding to the data slice that indicates the storage zone and the memory location is generated. A read request is received via the network from a requesting entity that indicates the data slice. The data slice is retrieved from the memory device based on the pointer, and is transmitted to the requesting entity.

Storing data sequentially in zones in a dispersed storage network

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

Intelligent cache with read destructive memory cells

A method includes receiving a piece of data at an upper-layer server of a multi-tiered storage system comprising the upper-layer server and a block server, and determining a signature for the piece of data. A first bloom filter stored on the upper-layer server is a copy of a second bloom filter stored on the block server. The first bloom filter is checked for the signature. When a match is found in the first bloom filter, the piece of data is sent for storage at the block server, and it is verified at the block server whether a match is present for the piece of data. When a match is present, the piece of data is deduplicated. When a match is not present, the piece of data is stored. When a match is not found in the first bloom filter, the piece of data is stored in the block server.

Deduplication in multiple-tiered storage systems

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Chicago, IL, United States of America

Praveen Viraraghavan