Fairchild Semiconductor Corporation

Praveen Muraleedharan Shenoy

Joseph Andrew Yedinak

Mark L Rinehimer

Christopher Boguslaw Kocon

Christopher Lawrence Rexer

Jaegil Lee

Chongman Yun

Dwayne S Reichl

Anup Bhalla

Hamza Yilmaz

James N Pan

Gary M Dolny

Richard L Woodin

Sampat Shekhawat

Douglas Joseph Lange

Jon Gladish

Hocheol Jang

Kwanghoon Oh

Rodney S Ridley, Sr

Harold Heidenreich

In one general aspect, a power device can include an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type. The power device can include a termination region surrounding at least a portion of the active region and can have a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type. Each of the plurality of pillars of the first conductivity type in the active region and the termination region can be defined by a trench. The power device can include an enrichment region at a bottom portion of one of the plurality of pillars of the first conductivity type in the active region.

Superjunction structures for power devices

An accumulation-mode field effect transistor including a plurality of gates. The accumulation-mode field effect transistor including a semiconductor region including a channel region adjacent to but insulated from each of the plurality of gates.

Accumulation-mode field effect transistor with improved current capability

In one general aspect, a power device includes an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width. The power device includes a termination region surrounding at least a portion of the active region and having a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width and are smaller than each width of the pillars of the second conductivity type in the termination region. The power device includes a transition region disposed between the active region and the termination region.

In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.

Superjunction structures for power devices and methods of manufacture

A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

A method of forming an accumulation-mode field effect transistor includes forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type. The channel region may extend from a top surface of the semiconductor region to a first depth within the semiconductor region. The method also includes forming gate trenches in the semiconductor region. The gate trenches may extend from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth. The method also includes forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.

Method for forming accumulation-mode field effect transistor with improved current capability

An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions.

Structure and method for forming accumulation-mode field effect transistor with improved current capability

A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device.

Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device

A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

Method of making a MOS-gated transistor with reduced miller capacitance

In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

MOS-gated transistor with reduced miller capacitance

A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxial layers support the blocking voltage of the diode, and each of the multiple epitaxial layers supports a substantial portion of the blocking voltage. Optimization of the thickness and dopant concentrations of at least the top two epitaxial layers results in reduced capacitance and switching losses, while keeping effects on forward voltage and on-resistance low. Alternatively, the SBD includes a continuously graded N-type doped region whose doping varies from a lighter dopant concentration at the top of the region to a heavier dopant concentration at the bottom.

Schottky diode structure to reduce capacitance and switching losses and method of making same

A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.

Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off

A semiconductor diode includes a first semiconductor layer including a dopant having a first conductivity type. A second semiconductor layer is adjacent the first semiconductor layer and includes a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of the first semiconductor layer. Adjacent the second semiconductor layer is a third semiconductor layer including a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of the second semiconductor layer. A fourth semiconductor layer is adjacent the third semiconductor layer and includes a dopant of a second conductivity type. Respective contacts are connected to the first and fourth semiconductor layers.

Soft recovery power diode

A trench MOS-gated device having an upper surface includes a substrate having an upper layer of doped monocrystalline semiconductor material of a first conduction type. A gate trench in the upper layer has sidewalls and a floor lined with a first dielectric material and a centrally disposed core that is formed of a second dielectric material and extends upwardly from the first dielectric material on the trench floor to contact an interlevel dielectric layer overlying the gate trench. The remainder of the trench is substantially filled with a conductive material that encompasses and contacts the core of second dielectric material. A doped well region of a second conduction type overlies a drain zone of the first conduction type in the upper layer, and a heavily doped source region of the first conduction type contiguous to the gate trench and a heavily doped body region of the second conduction type are disposed in the well region at the upper surface. The interlevel dielectric layer disposed on the upper surface overlies the gate trench and the source region, and a metal layer in electrical contact with the source and body regions overlies the upper surface and interlevel dielectric layer.

Growing community of inventors

Wilkes Barre, PA, United States of America

Praveen Muraleedharan Shenoy