Ambarella International LP

Praveen Kumar Jaini

Karthik Narayanan Subramanian

SriHari Raju Saripella

Hejia Yan

Hsin-Wu Hsu

An apparatus comprising a battery and a circuit. The battery may be configured to provide a persistent power source. The circuit may comprise a processor, self-test logic, internal storage and logic circuitry. The self-test logic may be configured to perform a status check to determine an operating status of the logic circuitry. The processor may be configured to enable a first portion of the status check to be performed during a shutdown of the apparatus and a second portion of the status check to be performed during a bootup of the apparatus. The battery may provide the persistent power source to the internal storage after the shutdown of the apparatus. Parameters generated during the first portion may be stored in the internal storage. The parameters stored in the internal storage may be used with the second portion to determine the operating status of the logic circuitry.

Smart storage of shutdown LBIST status

An apparatus includes a core logic circuit, one or more integrated clock-gating (ICG) cells, and one or more ICG control cells (ICCs). The core logic circuit generally comprises a plurality of flip-flops. The plurality of flip-flops may be connected to form one or more scan chains. Each of the one or more integrated clock-gating (ICG) cells may be configured to gate a clock signal of a respective one of the one or more scan chains. Each of the one or more ICG control cells may be configured to control a respective one or more of the one or more ICG cells.

Unified approach for improved testing of low power designs with clock gating cells

An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a launch signal synchronized with a first clock signal in a first clock domain. The second circuit may be configured to (i) receive a second clock signal in a second clock domain and (ii) generate a plurality of pulses in each of a third clock signal and a fourth clock signal based on the second clock signal and the launch signal. A frequency of the pulses in the fourth clock signal may be an integer multiple of another frequency of the pulses in the third clock signal. An initial one of each of the pulses in the third clock signal and the fourth clock signal may be synchronized with each other.

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Sunnyvale, CA, United States of America

Praveen Kumar Jaini